FSM - single process vs dual process performance comparation

Hello,

FSM A is designed using a single VHDL process - hence it's completely synchronous.
FSM B is designed using a 2 VHDL processes - hence it's outputs are combinatorial.

In theory, FSM A should allow higher Fmax... but (as an experiment) what if we register the outputs of FSM B ?
Is it safe to assume that both FSMs will have the same Fmax ?

No - the logic may be completly different.

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Why not compile the two - and find out?

The normal FPGA architecture today is combinatorial logic followed by a register. That is perfect for a single process FSM.
It is also a good design policy to only have registered outputs from a block.

I see absolutely no reason to use a two-process FSM today. It has no advantage and it makes the code much harder to read.
I don't think it is possible to say in general that a 2-process FSM with added output registers will be faster or slower, but I think it will use more registers.

I see absolutely no reason to use a two-process FSM today.

Click to expand...

Latency ?

but I think it will use more registers.

Click to expand...

If a DFF implementation is defined as a signal under a clocked process - I can't think of a reason for that to happen. The amount of registers isn't ambiguous...

Simple example in planahead with FSM_B output buffered gives the same logic implementation as one process FSM. (new_parseer on with spartan-3AN choosen).

The drawbacks of using two state FSM is IMHO:
- you get more hard to read code
- 1 clk latency less for much higher output delay time = in the end lower system performence ( in my simple example output delay difference is higher then clock cycle [but its i/o planning dependend]).
- cant really divide system for a team, because as the outputs are not registered, its hard to divide code for partitions hence write proper constants.
- if latch output registers are in higher/lower in hierarchy entity blocks, not forcing flatting the hierarchy might implement different not optimal FSM compared with one state FSM

allin all two state FSM is quite useless

If FSM B has registered output logic then as long as the FSMs are identical (i.e. the outputs have identical timing and responses to inputs) the two FSMs should have synthesis results that should be identical. If they aren't the same then you are likely looking at some sort of boolean reduction algorithm issue with the synthesis tool. If they aren't registered and you have identical output timing then you will have two entirely different implementations with the FSM B having much worse Fmax due to the combinational paths.

Might be interesting to make a suite of FSM descriptions (small, medium, and large) to test this out and see if there are any differences between the various synthesis tools (e.g. Synplify, Leonardo, XST, Quartus-II, Vivado) might be very useful to know what is the optimal method of describing an FSM for each tool depending on the complexity of the FSM.

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Come to think of it, this might be an excellent school project. Determine the results of the following matrix: HDL language, FSM complexity, Synthesis tool. That's like 30 combinations