fsm design in verilog

Status
Not open for further replies.
A

arya.jagadeesh

Member level 2
Joined
Jul 16, 2013
Messages
44
Helped
4
Reputation
8
Reaction score
4
Trophy points
8
Location
INDIA
Visit site
Activity points
285
in moore type fsm

Code Verilog - [expand]
1
2
3
4
5
6
7

always@(.....)
 
begin
writnig steates transition code
 
z= (state variable== some state)
end


i found there is difference if i keep assignment outside the always block.....how this is happening why signal is delayed in first case
 
Last edited by a moderator: 

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

modulesimple (Clock, Resetn, w, z);
input Clock, Resetn, w;
outputz;
reg [2:1] y;
parameter[2:1] A = 2’b00, B = 2’b01, C = 2’b10;
// Define the sequential block
always@(negedgeResetn orposedgeClock)
begin
if (Resetn == 0) y<=A;
else
case(y)
A: if(w) y<=B;
else y<=A;
B: if(w) y<=C;
else y<=A;
C: if(w) y<=C;
else y<=A;
default:y<=2’bxx;
endcase
// z=(y==c); output at this is one clock cycle after y changes to c,z here is reg
end
// Define output
assignz=(y==C); output at this becomes one at same time as y changes to c
endmodule
 
Last edited by a moderator:

First assignment between endcase and end is a registered output.
Second assignment between end and endmodule is a combinatorial output.

What don't you understand? The behavior is correct as you stated in your original post.
 

    V

    Points: 2
    Helpful Answer Positive Rating
hi arya
first assignment is in always block and that's and u have used non blocking state ment that's why it is updating after one clock.. if u see synthesis it will come out from a flop
and one is continuous statement hence it will update as the transaction is done if u synthesis rtl it will be from combinational circuit..

I hope u will get ur all answer by this paragraph

Thanks and Regards
VIr_1602
 

    V

    Points: 2
    Helpful Answer Positive Rating
thank you for your reply
i have a question with registerd outputs

in general, all the assignments values are updated in the next clock?
 

Hi arya

Thats what the sequential circuit means.

Regd
Vir
 


Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…