From Cadence Virtuoso to Silicon Ensemble

silicon ensemble

I've done a layout using Cadence Virtuoso and I want to export it to Silicon Ensemble to connect it with another design. Does anybody know how can I do it?
Thanks

silicon ensemble cadence user manual

You can export that using LEF format. See Tools -> Export. There should be LEF export option.

virtuoso lef export

Thank you for the response but I prefer to export it to verilog because it would be easier for me to connect both designs. Another possibility would be export it to DEF but I don't know how to connect a verilog file and a DEF one. Can anybody help me, please?
Thanks

silicon ensemble layout abstract

It impossible to transfer layout to verilog. Besides both of the tools you mentioned are layout tools. Silicon Ensemble need information about your block layout. How can you transfer this information using verilog?

silicon ensemble 与 virtuoso

I've done a digital design usign a verilog description of the circuit with a LEF file where the standard cells are declared. So, it's possible to use verilog files.

lef format

If you use standard cell you don't need develop layout with Virtuoso. Silicon Ensemble can accept your Verilog netlist.

Maybe, I haven't explained it properly. I've done two designs: a digital one with standard cells and an analog one. I've used Silicon Ensemble to do the digital design and Cadence Virtuoso for the analog one. Now, I want to connect both designs using Silicon Ensemble because I think it's better than doing it with Cadence Virtuoso. To use Silicon Ensemble I need to export the analog design to another format that Silicon Ensemble can recognize. I've tried to export the layout view of the analog design to DEF and LEF but there are some errors during the importation in Silicon Ensemble. I don't know if I can export it to verilog, probably it's impossible to do it because a verilog netlist doesn't have the information of a layout view.
The question is: How can I connect both designs using Silicon Ensemble?
Thanks

Can you post us the errors reported by SE ?
Sounds there is a mismatch between your analog verilog descriptions (manually written and included in your verilog netlist!!!) and your DEF/LEF description.

All the errors are the same one: Silicon Ensemble doesn't recognize the components that are described in the file.
When I export to DEF, components are name with numbers that don't have any sense, instead of naming them with the appropiate cell name.

You should use abstract or abgen to translate your layout to one verified LEF which one SE could accepted.