frequency multipliers - some questions

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djalli

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frequency multipliers

I want to multiply the frequency of a signal. If the signal I will generate is at range 0.5Hz to 5Hz how I would multiply 10, 100 times this frequency. Imagine the signal I am is amplifying easily in amplitude with OP-97 IC which uses very little current resulting of a low power consumed which is my biggest concern.

thank you all.
 

Re: frequency multipliers

If you have control of the generation of the signal, generate it at the highest value (100x) and divide down with CMOS logic. It is usually desirable that the final division is by 2 to get a square wave.
 

Re: frequency multipliers

flatulent said:
If you have control of the generation of the signal, generate it at the highest value (100x) and divide down with CMOS logic. It is usually desirable that the final division is by 2 to get a square wave.
Click to expand...

flatulent you know what is the worst part? Imagine if would someday in real world I will operate with a signal 0.5Hz to 5Hz.
I have heard about these frequency multipliers but not at very small ranges.
 

Re: frequency multipliers

This is a real problem. The worst part is the 10-1 range of your basic signal.

If you have some power to burn, use a PLL with a divider 100 or 10 in the output between the VCO and the frequency phase detector. You will have to use a very narrow loop filter well under 0.01 Hz which will make the loop response very slow.

Another method is to use some form of DSP to measure the frequency and generate a multiiple of it.
 

Re: frequency multipliers


My first intention was to use DSP fft as the only method viable but yes power is real concern. It is something it concerns everybody. I am heading for chips because of their compact size. Later I can optimize the circuit. Is any web reference, sample I can refer for frequency multiplying and it does not matter as of now if it is 1Hz or 1kHz?

flatulent my god thank you so much for this help. You gave me another bright alternative as using PLL. Thank you so much.
 

If you can properly detect zero crcosing for 0.5 - 5 Hz
you can use counter to calculate number of 100 Hz pulses and use this value to load into another counter
(counter with parallele loading ) . This will define variable divisor factor based on low frequency signal
frequency . Use high frequency input to count second counter .
If freq for first counter is 100 Hz and freq for second counter is 1 MHz , division factor will be 10000. But there could be problem with phase noise on multiplied signal
 

Re: frequency multipliers

if there is already a uP in your system , why not use it as some kind of dsp ?
 

Re: frequency multipliers

jlm said:
if there is already a uP in your system , why not use it as some kind of dsp ?
Click to expand...

I am thinking any exact DSP filter and since I am not finding one I am assuming better to multiply the frequency, Please advise me
 

Re: frequency multipliers

I think that the pll with frequency divider in the feedback path and with very low loop bandwidth and hogg type of the phase detector (Clock Data recovery type) will be most viable option.
Other option will be to use Delay lock loop (DLL) and then use the phase interpolator to multyply the ouput clock but in this case there will be two issues
1) Input clock jitter should be very low.
2) And the design of the phase interpolator will be very critcal part.
Now its depends on you to do the tradeoff between the power consumption and ouput clock jitter.

Cheers
Amit Bhaiji
 

Re: frequency multipliers

if you need mutily then big, pll is the only way. if you need to double it, the mixer is also one way.
 

Re: frequency multipliers

You could probably use a clock source eg.555 to generate 500 Hz for the x 100 and a counter to generate 50 Hz for the x 10, then use your singnal(0.5 hz ~ 5 hz pulse) to control an analog switch to control the output for either x 10 or x 100. Thats probably the simplest way to do it, if all you want it a fix multiplication factor instead of sweeping.
 

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