frequency multiplier using Xilinx System Generator

I want to make a frequency multiplier (60 Hz input frequency, output frequency of 120 Hz) using an FPGA (Spartan 3E).
Can anyone help me with an example of whether or not you can do this. I already check that can be done with a DPLL but it is very difficult to implement.

Can you just generate a 120 Hz in the FPGA and synchronize it with the input? or is your input frequency going to vary?

If doubling a 60 Hz input is all you want then you could consider just using a diode doubler. No need for the fpga.

As for your original question... The best match is probably to use the DCM. Not sure if the spartan 3E accepts such a low frequency though, you'd have to check the datasheet for that. Anything PLL is right out since 60 Hz is too low for fpga PLL's. But DCM maybe.

And just as a totally random observation .. .if this 60 Hz happens to be power mains related ... be sure to 1) use isolation, and 2) did I mention diode doublers?

There's no significant difference between a Xilinx DCM and what other vendors name PLL, also in term of frequency range. The minimum input frequency (actually the minimum PFD operation frequency) is at least several MHz.

Thanks for the replies, what I do is a voltage regulator and I need to generate PWM to control two MOSFETs, the main idea is to have all the control block in the Spartan 3E, measured from the mains voltage (120 Vpp 60Hz ) and are processed within the FPGA.

Then from there the need for a frequency multiplier to generate PWM modulation (the frequency of the carrier signal must be higher than the frequency of the modulating signal), I will test whether it exists as with DCM, but if anyone can help me with a tutorial or something would be helpful.

I find it interesting besides generating the FPGA 120 Hz and synchronized with the input signal, but can help me with an example or a tutorial.
I already try designing a digital PLL in simulink and then wanted to convert it to VHDL using "Simulink HDL coder", but gave me a lot errors and can not seem to fully implement in the FPGA, you need an external VCO.

Best Regards

Review this document https://www.xilinx.com/support/documentation/application_notes/xapp462.pdf and can not seem to generate such low frequencies to the FPGA DCM.

My question now is: I can work with 120 Hz signals in the FPGA?

Basically an all-digital PLL (ADPLL) can be a solution to your problem.

You didn't mention the intended output waveform of the PLL. In power electronic applications, a 50/60 Hz PLL with quadrature sine output is a common building block. It can be implemented with a NCO, phase detector (multiplier with averager/integrator) and a PI controller. In contrast to the high frequency analog PLL provided for FPGA clocking, the complete PLL function is performed by digital signal processing. Thus it's called digital or all digital PLL (DPLL/ADPLL). Details can be found in literature, e.g. Roland E. Best, Phase-Locked Loops, Design, Simulation and Applications.


All Digital Phase-Locked Loop (ADPLL)

The input waveform and output frequency synthesizer (PLL divisor + N) are square waves, the sine wave in an external circuit is transformed to square using a comparator,
In the FPGA control system performed as described below:
The frequency of 60 Hz square wave signal is converted into a signal with frequency of 120 Hz, this signal then turn it into triangular.
Triangular triangular signal is compared to a DC signal measurement of the electrical network to form the PWM.

Can I do this?

I have a DPLL designed in simulink and I was wondering if anyone can suggest a way to design in VHDL using "Simulink HDL coder" of Matlab

Best Regards

What you describe sounds like simple phase angle control, not PWM. Why do you need a PLL? Can't you start the triangle at both zero crossings? That's how most analog phase angle control systems, e.g. TCA785 work. There are many ways to implement a similar function in digital signal processing in a FPGA.

Thanks for your help, do what you suggested, and the truth is not so complicated.

A friend asked me a question and wanted to have your opinion

It is possible to develop an ATA controller using FPGA, I have seen some development kits with SATA connection, which is that if not within the programmiglogic of these kits bring embedded somehow or some kind of support ATA commands. I've also read in this topic to recommend some brands like ALTERA
If anyone has experience with this I would appreciate your help.

If anyone has experience with this I would appreciate your help.

I understand that you're asking for an ATA controller, not the interface. PATA interface is regular TTL level logic and can be easily handled by FPGAs, possibly needing some level translation. SATA can be handled by most recent FPGAs with serial GBit transceivers. SATA is however involving complex logic, the respective logic designs (IP cores) are rather expensive.

The ATA/IDE interface already offers read and write sector commands, a basic controller would possibly add data buffering, that's no problem for a FPGA design. If it goes to file systems, most design examples are passing the task to a software processor. Only for limited puposes, e.g. reading a bootsector, it would be reasonable to implement the function in a HDL design.