natdon11
Newbie
Hi plz bare with me as i am a bit of a novice when it comes to verilog.
I have been tasked with producing a frequency divider implemented in verilog from a counter module that I have made earlier. The idea being the counter counts to a set value then resets, when that happens it toggles an output which is the divided signal.
My counter module: (this counts to its max number on the 24 bits then resets.)
as you can the output of the counter is a register.
The issue i am having is when trying to instantiate this module inside my frequency divider module:
I need to be able to access the output from the counter module "out" however I realised that I couldn't connect a register straight to the output of the previous module. So a tried to connect it to a wire then update new register with the value on that wire. However this has caused me all sorts of errors. So my question is how to I set up my clock divider module, So that I can access the output register of binary counter and use it to toggle an output when it reaches a certain value.
The current error I am getting is:
Error (10200): Verilog HDL Conditional Statement error at ClockDivider.v(22): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct.
marked in the code.
Thanks in advamce for any help
I have been tasked with producing a frequency divider implemented in verilog from a counter module that I have made earlier. The idea being the counter counts to a set value then resets, when that happens it toggles an output which is the divided signal.
My counter module: (this counts to its max number on the 24 bits then resets.)
Code:
module nBitBinaryCounter(
input clk,
input rst,
output reg [23:0] out
);
always @ (posedge clk or negedge rst)
begin
if (rst == 1'b0)
out <= 1'b0;
else if (out == 23'd16777216)
out <= 1'b0;
else
out <= out + 1'd1;
end
endmoduleas you can the output of the counter is a register.
The issue i am having is when trying to instantiate this module inside my frequency divider module:
Code:
module ClockDivider(
input clk,
output reg clk_out,
output reg rst
);
wire [23:0] count;
reg [23:0] count_reg;
nBitBinaryCounter count1(
clk,
rst,
count
);
always @(posedge clk or negedge rst)
begin
count_reg = count;
if(count_reg == 24'd5000000) //line 22 error
begin
clk_out <= !clk_out;
end
else if (rst == 1'b0)
begin
clk_out <= 1'b0;
end
end
endmoduleI need to be able to access the output from the counter module "out" however I realised that I couldn't connect a register straight to the output of the previous module. So a tried to connect it to a wire then update new register with the value on that wire. However this has caused me all sorts of errors. So my question is how to I set up my clock divider module, So that I can access the output register of binary counter and use it to toggle an output when it reaches a certain value.
The current error I am getting is:
Error (10200): Verilog HDL Conditional Statement error at ClockDivider.v(22): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct.
marked in the code.
Thanks in advamce for any help