Frequency Divider from Counter module - verilog

[natdon11]

Hi plz bare with me as i am a bit of a novice when it comes to verilog.
I have been tasked with producing a frequency divider implemented in verilog from a counter module that I have made earlier. The idea being the counter counts to a set value then resets, when that happens it toggles an output which is the divided signal.
My counter module: (this counts to its max number on the 24 bits then resets.)

module nBitBinaryCounter(
    input clk,
    input rst,
    output reg [23:0] out
);


    always @ (posedge clk or negedge rst)
    begin
        if (rst == 1'b0)
            out <= 1'b0;
            
        else if (out == 23'd16777216)
            out <= 1'b0;
            
        else
            out <= out + 1'd1;
        
    end
endmodule

as you can the output of the counter is a register.
The issue i am having is when trying to instantiate this module inside my frequency divider module:

module ClockDivider(
    input clk,
    output reg clk_out,
    output reg rst
);

    wire [23:0] count;
    reg [23:0] count_reg;
    
    nBitBinaryCounter count1(
        clk,
        rst,
        count
    );

    always @(posedge clk or negedge rst)
    begin
        count_reg = count;
        if(count_reg == 24'd5000000) //line 22 error
        begin
            
            clk_out <= !clk_out;
        end
        
        else if (rst == 1'b0)
        begin
            clk_out <= 1'b0;
        end
        
    end
endmodule

I need to be able to access the output from the counter module "out" however I realised that I couldn't connect a register straight to the output of the previous module. So a tried to connect it to a wire then update new register with the value on that wire. However this has caused me all sorts of errors. So my question is how to I set up my clock divider module, So that I can access the output register of binary counter and use it to toggle an output when it reaches a certain value.
The current error I am getting is:
Error (10200): Verilog HDL Conditional Statement error at ClockDivider.v(22): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct.
marked in the code.
Thanks in advamce for any help

 

[FlyingDutch]

Hello,

it is not allowed to use posegde and negedge in one always event. Just alter the line with this event:

always @(posedge clk or negedge rst)

to:

 always @(posedge clk)

It will be working OK. You can consider checking the condition:

if (rst == 1'b0)

first.

Best Regards

 

[ads-ee]

Hello,

it is not allowed to use posegde and negedge in one always event. Just alter the line with this event:

always @(posedge clk or negedge rst)

to:

 always @(posedge clk)

It will be working OK. You can consider checking the condition:

if (rst == 1'b0)

first.

Best Regards

Actually the statement always @(posedge clk or negedge rst) is for a rising edge clock with an active low asynchronous reset and is correct.
It was correctly pointed out by @FlyingDutch that the reset statement should start the if statement not be in the else if.

The code as written compiles without errors in both Modelsim and Vivado, so I'm not sure why your are saying line 22 has an error.

You do have other issues in this code that need to be addressed.

1. Your reset rst in ClockDivider is declared as an output, so nothing is driving the reset in the design.
2. Your value in the compare out == 23'd16777216 is a 24-bit compare (out) to a 25-bit value (but declared to be a 23-bit constant) not sure exactly what the value being compared is.
3. You are using a blocking (=) assignment count_reg = count; in a edge sensitive (clocked) always block, mixing non-blocking (<=) and blocking (=) can cause synthesis/simulation mismatches. Use only non-blocking in a clocked always block and blocking assignments in combinational always blocks.
4. Don't use positional port connections when instantiating a module use named port connections, e.g. .clk (clk), Doing this will avoid issues with changes to the port order in the module being instantiated, i.e. a port is added to the module.

 

[KlausST]

Hi,

... and....

the new clock should not be used as a new PLD_internal clock (for other registers).. use clock_enable instead.

Klaus