Frequency difference measurement in 10 MHz region

[macellan]

Hi guys,

I' m searching for a relatively simple way to measure the difference between two signal sources. 10MHz and 10MHz + some hundred Hz difference is subject of my issue. I' m thinking about using a flip flop for this purpose or a comparator maybe. I don't have one in my hand and before ordering I would like ask for your opinions and possible other suggestions.

It would be helpfull also if you have suggestions for simulating these circuits. I' m trying on proteus right now but nothing appeared yet!

Any idea is appreciated ...

Thanks

 

[KlausST]

Hi,

XOR them.

Klaus

added:
This just gives a signal wich duty cycle gives the phase between both signals. Low pass filter it to get the lower frequency.

A single DFF will work if both duty cycles are close to 50%. If this isn´t the case you may add two DFF as 1/2 frequecny divider on each input.

If you do more such stuff I recommend to use a simulation software.

 

[BigBoss]

You may simply use a Mixer to obtain the frequency difference then measure how much there is..
Or, you can also use a Phase/Frequency Detector so that the output of this detector will be proportionally related to Input Frequencies.
Standard FFs can be used at 10MHz to realize the F/P Detector.

 

[schmitt trigger]

Heterodyning the signal with a mixer would also be the way I would follow.

Needless to say, with any path you choose to follow, the accuracy will be wholly determined by the reference frequency.

 

[FvM]

Compare frequencies or measure the difference?

 

[macellan]

First of all, thank you for your suggestions.

Hi,

XOR them.

Klaus

Dear Klaus,

I made some trials on Xilinx ISE 14.7 simulator and attached the result. Here I have generated two signals with 20 ms period and 16 ms period generating 16 cycle (62.5 Hz) and 20 (50 Hz) cycle respectively to match the total measurement time. Third signal is the output of XOR.

I'm thinkging that this very low frequency signal doesn' t make sense, because logic is logic. However, I can't see a signal having difference frequency (12.5 Hz) but bigger.

Bytheway XOR is a built in function of ISE 14.7. I just did x1 = a1 xor a2






Best wishes

 

[KlausST]

HI,

You siad:

10MHz and 10MHz + some hundred Hz

thus the frequency deviation is some 0.001% only.

now you test with 25% ... for sure this gives different results.

****
It still is not clear what output signal you expect.

I guess the DFF solution give the ouput you expect..
--> do a test with the DFF.

Klaus

 

[asdf44]

Unless you have real time or very high accuracy requirements a very easy solution is to simply count clocks over a given time period. One second would be a good choice, then pause the counter and you have your frequencies.

Because 10Mhz isn't very fast I'd consider an oversampling implementation and keep track of the remainder for some additional precision. Or at least make sure to count both edges.

 

[BradtheRad]

Clock #1 increments a counter. Clock #2 decrements it. (What counter can do the job? Not sure. Maybe a binary counter. Maybe a shift register. Maybe a charge bucket.) The counter jitters back and forth most of the time, but gradually it moves a few steps into the positive or negative, to tell you which clock is the higher frequency.

The counter must know what to do when it receives simultaneous increment and decrement.

 

[macellan]

HI,

You siad:

thus the frequency deviation is some 0.001% only.

now you test with 25% ... for sure this gives different results.

Here is latest sim. result using 1 MHz and 1.25 MHz. There is a counter connected to the output counting the rising edges of the XOR output. Expected result is 250kHz (it is the difference of two freq. inputs) but the result is 1.75 M, that's 1.75 MHz!



[/QUOTE]
****
It still is not clear what output signal you expect.

I guess the DFF solution give the ouput you expect..
--> do a test with the DFF.

Klaus[/QUOTE]

I' ll try DflipFlop after learning how exactly I must connect inputs and read the output.

I' ll let you all know the result. Thanks ...

 

[macellan]

You may simply use a Mixer to obtain the frequency difference then measure how much there is.. Or, you can also use a Phase/Frequency Detector so that the output of this detector will be proportionally related to Input Frequencies. Standard FFs can be used at 10MHz to realize the F/P Detector.

I don't exactly know what you mean by mixer. But I' m searching for a phase detector desing in VHDL. If you know where to find one and share a link that would be awesome. thank you.

 

[macellan]

Unless you have real time or very high accuracy requirements a very easy solution is to simply count clocks over a given time period. One second would be a good choice, then pause the counter and you have your frequencies.

Because 10Mhz isn't very fast I'd consider an oversampling implementation and keep track of the remainder for some additional precision. Or at least make sure to count both edges.

Well, I have two options as also you said (or what I understand from what you said):

- Count two sources up to 10^7 region and simply calculate the difference

- "Simply" get the frequency difference in a way and count up to ~10^3 region


I don' t want to work with such high frequencies (first option). So I'm forcing for the second option.

 

[KlausST]

Hi,

Here is latest sim. result using 1 MHz and 1.25 MHz

Again here you use 25% deviation. Why? Your initial post says about 0.001%. deviation. A factor of 25000! --> use meaningful simulation.

Additionally you missed my information:
* The output of the XOR gives a PWM that needs to be low pass filtered. --> The XOR output does not give the difference frequency.
Only the low pass filtered signal gives the deviation. .. but again: not with 25% frequency deviation.

* I told you to use the DFF solution.

It makes no sense to give response ... and you don´t care about it...

Klaus

 

[asdf44]

Well, I have two options as also you said (or what I understand from what you said):

- Count two sources up to 10^7 region and simply calculate the difference

- "Simply" get the frequency difference in a way and count up to ~10^3 region


I don' t want to work with such high frequencies (first option). So I'm forcing for the second option.

The frequencies are the same in both options....~10Mhz. It's the counters are different sizes.

Counters of 32bit are trivial in modern FPGA's from both a space and timing point of view (to the low 100's of MHz).


Brad: I'm suggesting two counters. One for each clock. Subtract them to get the difference.

 

[BradtheRad]

Brad: I'm suggesting two counters. One for each clock. Subtract them to get the difference.

Yes, that is the straightforward method.
However my idea (post #9) is to have one counter rather than two normal frequency counters. One clock enables the up direction (simultaneously adding 1), the other clock enables the down direction (simultaneously subtracting 1). A bidirectional counter might be capable (such as
74HC190 4-bit BCD decade Up/Down counter or
4029 4-bit Synchronous Up/Down counter).
The readout is the difference in frequencies.


There is the spec as to whether a change of state occurs at a rising edge or a falling edge. It may be a hurdle to enable up/down mode soon enough to handle an incoming clock pulse.

Tutorial about bidirectional counters:

www.electronics-tutorials.ws/counter/count_4.html

 

[macellan]

Hi,

It makes no sense to give response ... and you don´t care about it...

Klaus

I care about it but I didn' t get your point. Now it is clear. I just don' t know yet how to implement a low pass filter for such purpose. I' ll search and try. Thank you.

- - - Updated - - -

I'm suggesting two counters. One for each clock. Subtract them to get the difference.

This looks much easier. I' ll try it. Thank you for the response.

- - - Updated - - -

Yes, that is the straightforward method.
However my idea (post #9) is to have one counter rather than two normal frequency counters. One clock enables the up direction (simultaneously adding 1), the other clock enables the down direction (simultaneously subtracting 1). A bidirectional counter might be capable (such as 74HC190 4-bit BCD decade Up/Down counter or4029 4-bit Synchronous Up/Down counter).
The readout is the difference in frequencies.

There is the spec as to whether a change of state occurs at a rising edge or a falling edge. It may be a hurdle to enable up/down mode soon enough to handle an incoming clock pulse.

This is something different than so far I thought. At least this can be a nice exercise as well Thank you !