Frequency devider verilog code (50mhz to 75 micro second)

[no0ona]

Hi,

I have a divider have an input of 50mhz and the output is 75micro second. How I write the code for this divider in a Verilog?

 

[FvM]

75 us = 50*75 clock counts.

 

[no0ona]

75 us = 50*75 clock counts.

I didn't get what you means, can you explain your question

 

[rberek]

He didn't ask a question. He gave you some information. 75 us is 3750 clock periods at 50 MHz (I'm assuming it isn't 50 milliHertz as the diagram indicates).

So design a counter in Verilog that counts to 3750. When it gets there, it outputs a pulse, resets to zero and counts again. That will give you your 75us timing marker.

r.b.

 

[no0ona]

oh Thanks. But in my diagram the input is 50miliHerts and the output is 75micro second, so I think in the beginning I should change the frequency to time so it will be 20second.

And my question is how I can write the code in Verilog for the same diagram??

 

[rberek]

Firstly, you are going to have to decide what the actual design problem is. I think it is more likely that there is a typo on your diagram (i.e. should be 50 MHz rather than 50 mhz). 50 mHz and 75 us makes no sense, nor does 50 mHz and 20 seconds.

Secondly, I did explain how you can write Verilog code for this. This is a very simple Verilog exercise, and you should be able to find several examples in books, tutorials and on the internet. Take a shot at writing it and then ask specific questions if you get stuck.


r.b.

 

[FvM]

50 milliHz makes no sense at first sight. In any case you should sketch a timing diagram how input and output signals are related.

 

[code_slave]

Hi,

I have a divider have an input of 50mhz and the output is 75micro second. How I write the code for this divider in a Verilog?

Here is a thread that gives good insight….
https://electronics.stackexchange.c...vide-50mhz-down-to-2hz-in-vhdl-on-xilinx-fpga