lukegeorge
Newbie level 3
![Newbie level 3](/styles/images/ranks/alevel3.gif)
Dear all,
I'm new to this forum and also in the veriloga module design.
I'm trying to design a veriloga module in which I have to impose a simple Vin/Vout behavior, and I need to impose the frequency dependence in the law. I made something like this:
When I try to assign the f parameter (frequency) equal to freq in AC simulation inside ADS Schematic I got the following:
Improper frequency dependence in 'my_device' parameters.
What I'm missing ?
Thanks in advance,
Luke
I'm new to this forum and also in the veriloga module design.
I'm trying to design a veriloga module in which I have to impose a simple Vin/Vout behavior, and I need to impose the frequency dependence in the law. I made something like this:
Code:
module my_device(in,out);
input in;
output out;
voltage in,out;
parameter real f = 100.0;
real vout,vin;
analog begin
vin = V(in);
vout = vin * f;
V(out) <+ vout;
end
endmodule
When I try to assign the f parameter (frequency) equal to freq in AC simulation inside ADS Schematic I got the following:
Improper frequency dependence in 'my_device' parameters.
What I'm missing ?
Thanks in advance,
Luke