LASI from (I think) Idaho State has layout and DRC, but
no LVS capability. It can produce a SPICE netlist from the
layout, which a third party SPICE:SPICE netlist compare
tool could use for LVS. There are only a few foundries that
have pre-existing support.
Electric is fully featured but will only work right for designs
created inside that tool; it uses an "arc" construct which
(last I looked) still could not be regenerated from a GDS-II
polygon-pile, so unsuitable for an after-the-fact, sourced
from some other tool, verification.
The PARIS/MGEN suite is out there, purported to be a fully
capable design tool from some European semiconductor
company "back in the day", but I see zero activity on the
sourceforge pages and nobody talks about it at all.
That's about it, for free stuff.
You really need to think about what foundry / PDK, because
without that data in a form you can use or translate with
ease, all tools are equally useful. That is to say, 0=0.