Measured over a longer time interval, the output frequency stability of the PLL is the same as of the reference signal.
If using a PLL you will also have to use a low-pass filter. Making the cut-off frequency of the filter higher will result in less phase-noise, but it will also lead to a larger amount of spurs from the reference frequency in the output signal of the PLL. Lowering the filter's cut-off frequency will make the PLL to be slower in adapting to changes of the reference frequency or division ratio (for example, if you want to have a PLL that can change it´s output frequency to various multiples of the reference frequency, then when changing that multiple the output frequency will take longer to stabilize).
To design a PLL is thus a question of compromising. You can not have a PLL that is excellent in every aspect so you will have to sacrifice performance in one area to gain performance in some other area.
Motorola once made a chip named MC4044. It was a PLL-chip and the associated data-sheets held a lot of useful information regarding the design of a PLL in principle, including the low-pass filter.
/Pim