Hi,
most FPGAs are empty on power up. All I/Os are on default state (read FPGA documentation).
After power up they read their configuration from external memory. This takes some time. (maybe in your case the 28ms)
When you defined "clock" and some "outputs" ... then they are not valid immediately after power up, they are valid after the configuration is loaded.
If you want to get valid signals much earlier, then you need to do this
* either with external pullup / pulldown
* or using the FPGA´s line that tells whether the FPGA is configured or not.
For example if you have a microcontroller to communicate with the FPGA, then
* you can either generate a mcu_reset from the FPGA_ready (or similar name) = safe method
* or use a software_poll to wiat for the FPGA to get ready
* or just use a software delay (least safe method)
Klaus