dpaul
Advanced Member level 5
Hi,
I am trying to understand the exact communication stages between a 7 Series AMD FPGA and an external SPI Flash memory. The FPGA is configured to work in Master Serial Peripheral Interface (SPI) flash configuration mode x4, because at the bitgen.xdc I have set the following:-
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
I am referring to the UG470.
I read in there that the FPGA SPI first tries a read command in x1 and then in x2 and next in x4.
But I failed to find a detailed description of the exact sequence of operations and data exachange.
Can anyone help me to find one?
I am trying to understand the exact communication stages between a 7 Series AMD FPGA and an external SPI Flash memory. The FPGA is configured to work in Master Serial Peripheral Interface (SPI) flash configuration mode x4, because at the bitgen.xdc I have set the following:-
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
I am referring to the UG470.
I read in there that the FPGA SPI first tries a read command in x1 and then in x2 and next in x4.
But I failed to find a detailed description of the exact sequence of operations and data exachange.
Can anyone help me to find one?
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