[SOLVED] FPGA SPI-Flash communication

[dpaul]

Hi,

I am trying to understand the exact communication stages between a 7 Series AMD FPGA and an external SPI Flash memory. The FPGA is configured to work in Master Serial Peripheral Interface (SPI) flash configuration mode x4, because at the bitgen.xdc I have set the following:-

set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

I am referring to the UG470.

I read in there that the FPGA SPI first tries a read command in x1 and then in x2 and next in x4.
But I failed to find a detailed description of the exact sequence of operations and data exachange.

Can anyone help me to find one?

 

[aliarifat794]

Have you thoroughly checked the docs here?

AMD Technical Information Portal

docs.amd.com

 

[dpaul]

That was the intention of my post.............which other docs or specific ports of a doc should I refer to for more understanding!

 

[pbernardi]

I find this page, maybe it helps: https://support.xilinx.com/s/article/65171?language=en_US

EDIT: not sure really, this is AXI related... maybe it just a completely different thing.

 

[dpaul]

@pbernardi
you completely misunderstood!
AXI had nothing to do when a FPGA is loading BS from Flash.