Big FPGAs can pull over 10A on the low voltage main core rail.
This is of course very config and application dependent. They
also assert in some cases, pretty fussy sequencing / ratiometric
behavior at power-up and power-down.
A "shrink fit to specific FPGA" power solution would (one hopes)
have taken care of these "secondary" issues and provide some
close-in layout style and BOM guidance, all of which will be
handy. At 0.9V core you will have about 50mV of "recommended"
tolerance on the rail and 200mV from nominal you'll see damage
(high) or retention loss (low) on SRAM cells - at least, according
to datasheets. There's doubtless some padding. You don't get
to know how much. So, 50mV/10A=5mOhm from POL filter / FB
(and ground, coming back) total layout resistance. And that's
if you're of a mind to allow near-low-limit supply sag.
Study the eval board layouts you can find Gerbers for, to get
ideas about routing priorities, styles, placement, weights & widths,
etc.