FPGA Look-up tables and Muxes

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journeyman200

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Look-up tables and Muxes

So I need to build a 8 to 1 MUX with any number of 4-input look up tables. The structure of the LUT is similar to this but with the extra select bit and 8 extra values.

The answer I was given is to turn the LUTs into 2:1 muxes and use 7 of them. 4 to contain the values, 2 to select between the 4 muxes, and 1 to select between the 2.

However, I'm confused because isn't the LUT basically a mux? It's a 4-input LUT so it has 16 possible values, which is more than an 8-1 mux has. So why can't I just use 1 LUT?

Thanks for any help.
 
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