FPGA LCD Text that changes depending on the mode

MICHIN · Tuesday at 5:34 AM

I need some helps!
What's wrong here that doesn't work as I want?

Code Verilog - [expand]
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[/
    wire                    clk_nco;
    textgen_nco
    #(
        .FREQDIV            (50000000           )
    )
    u_textgen_nco(
        .o_clk              (clk_nco            ),
        .i_clk              (i_clk              ),
        .i_rstn             (i_rstn             )
    );
    localparam  MODE_CLOCK_OPR =    2'b00;
    localparam  MODE_CLOCK_SET =    2'b01;
    localparam  MODE_ALARM_SET =    2'b10;
    always @(posedge clk_nco or negedge i_rstn) begin
        if (!i_rstn) begin
            o_line_data_valid <= 0;
            {o_line_data1, o_line_data2} <= 128'd0;
        end else begin
            case (i_mode_lcd)
                MODE_CLOCK_OPR: begin
                    o_line_data_valid <= 1;
                    {o_line_data1, o_line_data2} <= line_dataset[0];
                end
                MODE_CLOCK_SET: begin
                    o_line_data_valid <= 1;
                    {o_line_data1, o_line_data2} <= line_dataset[1];
                end
                MODE_ALARM_SET: begin
                    o_line_data_valid <= 1;
                    {o_line_data1, o_line_data2} <= line_dataset[2];
                end
                default: begin
                    o_line_data_valid <= 0;
                    {o_line_data1, o_line_data2} <= 128'd0;
                end
            endcase
        end
    end
endmodule
]

FvM · Tuesday at 8:01 AM

What are you expecting? How do you determine that the code is "not working", show your test bench.

dpaul · Tuesday at 8:01 AM

@MICHIN
What's wrong here that doesn't work as I want?
Write a test-bench, simulate your design and see what comes up!

MICHIN · Tuesday at 8:03 AM

FvM said:
What are you expecting? How do you determine that the code is "not working", show your test bench.

I am making a digital clock, and when I press switch 0 on the digital clock, the order changes to mode clock operation, mode clock setting, and mode alarm setting. And these changing modes should be displayed as they are on the text LCD. What should I do?

--- Updated Tuesday at 8:37 AM ---

FvM said:
What are you expecting? How do you determine that the code is "not working", show your test bench.

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[/
`include    "textgen.v"
module tb_textgen;
    // Inputs
    reg [1:0] i_mode_lcd;
    reg i_clk;
    reg i_rstn;
    // Outputs
    wire o_line_data_valid;
    wire [16*8-1:0] o_line_data1;
    wire [16*8-1:0] o_line_data2;
    // Instantiate the textgen module
    textgen
    u_textgen(
        .o_line_data_valid(o_line_data_valid),
        .o_line_data1(o_line_data1),
        .o_line_data2(o_line_data2),
        .i_mode_lcd(i_mode_lcd),
        .i_clk(i_clk),
        .i_rstn(i_rstn)
    );
    // Clock generation
    always begin
        #5 i_clk = ~i_clk; // 100MHz clock
    end
    // Stimulus
    initial begin
        // Initialize inputs
        i_clk = 0;
        i_rstn = 0;
        i_mode_lcd = 2'b00; // Start with MODE_CLOCK_OPR
        // Apply reset
        #10 i_rstn = 1;
        // Test case 1: MODE_CLOCK_OPR
        #10 i_mode_lcd = 2'b00; // Set mode to clock operation
        #100; // Wait for a few clock cycles
        // Test case 2: MODE_CLOCK_SET
        #10 i_mode_lcd = 2'b01; // Set mode to clock set
        #100;
        // Test case 3: MODE_ALARM_SET
        #10 i_mode_lcd = 2'b10; // Set mode to alarm set
        #100;
        // Test case 4: Default case (no mode)
        #10 i_mode_lcd = 2'b11; // Invalid mode
        #100;
        // End simulation
        $finish;
    end
    // Monitor output signals
    initial begin
        $monitor("At time %t, o_line_data_valid = %b, o_line_data1 = %h, o_line_data2 = %h",
                 $time, o_line_data_valid, o_line_data1, o_line_data2);
    end
    reg [8*32-1:0] vcd_file;
    initial begin
        if ($value$plusargs("vcd=%s", vcd_file)) begin
            $dumpfile(vcd_file);
            $dumpvars;
        end else begin
            $dumpfile("wave_text.vcd");
            $dumpvars;
        end
    end
endmodule
]

--- Updated Tuesday at 8:38 AM ---

dpaul said:
@MICHIN
What's wrong here that doesn't work as I want?
Write a test-bench, simulate your design and see what comes up!

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`include    "textgen.v"
module tb_textgen;
    // Inputs
    reg [1:0] i_mode_lcd;
    reg i_clk;
    reg i_rstn;
    // Outputs
    wire o_line_data_valid;
    wire [16*8-1:0] o_line_data1;
    wire [16*8-1:0] o_line_data2;
    // Instantiate the textgen module
    textgen
    u_textgen(
        .o_line_data_valid(o_line_data_valid),
        .o_line_data1(o_line_data1),
        .o_line_data2(o_line_data2),
        .i_mode_lcd(i_mode_lcd),
        .i_clk(i_clk),
        .i_rstn(i_rstn)
    );
    // Clock generation
    always begin
        #5 i_clk = ~i_clk; // 100MHz clock
    end
    // Stimulus
    initial begin
        // Initialize inputs
        i_clk = 0;
        i_rstn = 0;
        i_mode_lcd = 2'b00; // Start with MODE_CLOCK_OPR
        // Apply reset
        #10 i_rstn = 1;
        // Test case 1: MODE_CLOCK_OPR
        #10 i_mode_lcd = 2'b00; // Set mode to clock operation
        #100; // Wait for a few clock cycles
        // Test case 2: MODE_CLOCK_SET
        #10 i_mode_lcd = 2'b01; // Set mode to clock set
        #100;
        // Test case 3: MODE_ALARM_SET
        #10 i_mode_lcd = 2'b10; // Set mode to alarm set
        #100;
        // Test case 4: Default case (no mode)
        #10 i_mode_lcd = 2'b11; // Invalid mode
        #100;
        // End simulation
        $finish;
    end
    // Monitor output signals
    initial begin
        $monitor("At time %t, o_line_data_valid = %b, o_line_data1 = %h, o_line_data2 = %h",
                 $time, o_line_data_valid, o_line_data1, o_line_data2);
    end
    reg [8*32-1:0] vcd_file;
    initial begin
        if ($value$plusargs("vcd=%s", vcd_file)) begin
            $dumpfile(vcd_file);
            $dumpvars;
        end else begin
            $dumpfile("wave_text.vcd");
            $dumpvars;
        end
    end
endmodule

dpaul · 2024-11-13T20:59:03+0000

@MICHIN
You have shared with us your project requirements (which is probably given to you by your teacher) and your code.

But did you compile your design and get a problem?
The simulator tool is a complier of the testbench and the DUT and tells you if something is wrong or if it compiles correctly, will show you if your DUT is behaving the way as it should.
For me it is not possible to create a project and compile the design for you to find out your mistakes. That is your task!
Find it out and then come back here with specific problems giving adequate information.

FPGA LCD Text that changes depending on the mode

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FPGA LCD Text that changes depending on the mode

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