FPGA feasibility study help

[yyyyyy]

I am newbie of FPGA, and assigned to do some FPGA feasibility study recently. The target FPGA device is Xilinx Vertex II series. The most concerns I have are:
1. Since the logic design is pretty big, say 500k gate counts, How to estimate if my logic design can fit in Xilinx FPGA?
2. The logics is designed to work at 100MHz, I know it's impossible to work as this fast in FPGA, so what's the maximum frequency my deisgn can run in FPGA?
3. For Multimedia implementation, for example, Graphic accelerator, does it make sense to implement it in FPGA? since it requires a very high working frequency?
4. For a FPGA feasibility study, what should be taken into account typically?

Thanks in advance

 

[Renjith]

I am newbie of FPGA, and assigned to do some FPGA feasibility study recently. The target FPGA device is Xilinx Vertex II series. The most concerns I have are:
1. Since the logic design is pretty big, say 500k gate counts, How to estimate if my logic design can fit in Xilinx FPGA?

Hi,
VirtexII series FPGAs r having a very high gate count of 10 million gates,
then why do u want to bother about a design which consumes only 500 k only.
U can use xc2v500, which has got 500k gate count.

2. The logics is designed to work at 100MHz, I know it's impossible to work as this fast in FPGA, so what's the maximum frequency my deisgn can run in FPGA?

U meant to say FPGA can never achieve a speed of 100 Mhz?
Sorry u r wrong,now u might have to do a good reading of the manuals and datasheets of FPGAs. FPGA is built with CLBs which will boil down as LUTs in the device. The speed at which ur design has to work, purely depends on the number of logical levels in your design. i'e how many LUTs,interconnect lines,CarryChains in your critical path determines your maximum frequency.
For achieving a higher speed, u can go for pipelining,register duplication etc...

 

[yyyyyy]

Virtex II does have 10Milloin gate counts, but FPGA gate counts is different from the ASIC gate counts. I do see some previous design that 500K ASIC gate count logic plus memory turned out to be 5 million FPGA equvialent gate counts. I feel it's tricky to talking about gate counts when determining the FPGA capacity.

About the max frequency, I still have the question: how to estimate the best frequency my logic should work at in FPGA?

Thanks!

 

[Renjith]

About the max frequency, I still have the question: how to estimate the best frequency my logic should work at in FPGA?

Thanks!

To estimate this u have to find the critcal path in ur design, and try to analyse this logic when implemented using a 4i/p LUTS. and c how mnay LUTS will b coming in ur critical path. This is laborious task, and quite complex.

if u want to increase ur design frequency.
pipeling is a good technique to do that.
xilinx gives good docs to improve this.
u can do register insertion and signal duplication(to decrease the high fanouts).