tzushky
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fpga design model questions
Hello,
i am currently struggling to discover to build a complete fpga top for the system I need. first of all I know what I want it to do but i don't quite have fpga habits to get there as i should.
My basic questions are of the sort: I know i need an SRAM module, do i define this entity (it's vhdl i'm using ) or use fpga ressources(using xilinxvirtex 5)
I need some registers, how do i create them and how do i read/write them and use their value to manipulate my system state.
Which brings me to Finite state machines.
So, basically, i'm not exactly an FPGA developer but I'm trying to learn and don't know where to turn. ISE xilinx models don't help, they have no comments. simple examples in vhdl books don't help because i can say it's not vhdl syntax or habits which hold me back.
I also want to put an ahb slave because the system will be pilotedfrom elewhere later...
lots of pieces which i can see functioning in my head, i imagine theblocks and wires, and yet for simple things such as the SRAM , i don't know how to make this block, plus accesses from different modules (includingahbto them)
This is why i turn to you...Can you help me with some very practical advice or pieces of code from which i can understand once and for all how an fpga designer does it?
thanks in advance,
T
Hello,
i am currently struggling to discover to build a complete fpga top for the system I need. first of all I know what I want it to do but i don't quite have fpga habits to get there as i should.
My basic questions are of the sort: I know i need an SRAM module, do i define this entity (it's vhdl i'm using ) or use fpga ressources(using xilinxvirtex 5)
I need some registers, how do i create them and how do i read/write them and use their value to manipulate my system state.
Which brings me to Finite state machines.
So, basically, i'm not exactly an FPGA developer but I'm trying to learn and don't know where to turn. ISE xilinx models don't help, they have no comments. simple examples in vhdl books don't help because i can say it's not vhdl syntax or habits which hold me back.
I also want to put an ahb slave because the system will be pilotedfrom elewhere later...
lots of pieces which i can see functioning in my head, i imagine theblocks and wires, and yet for simple things such as the SRAM , i don't know how to make this block, plus accesses from different modules (includingahbto them)
This is why i turn to you...Can you help me with some very practical advice or pieces of code from which i can understand once and for all how an fpga designer does it?
thanks in advance,
T