Yes as far as I know as well, they are hard-coded in the bit file but while searching I found the following link,
may be you might get some help with this,
**broken link removed**
find the following code here and read it, I am not sure I just give a glimpse to it, but I guess you can alter the resistor value using tmp variable, by setting conditions to it...!
Code:
ARCHITECTURE str OF pulup_ex IS
COMPONENT pullup
PORT(o : OUT std_logic);
END COMPONENT;
COMPONENT IBUF
PORT(i : IN std_loigc;
o : OUT std_logic);
END COMPONENT;
SIGNAL tmp, core_in : std_logic;
BEGIN
tmp <= inpad1;
pu : pullup PORT MAP (tmp);
in : ibuf PORT MAP (tmp, core_in);
END str;
With some FPGAs/CPLDs, you can approximate a controlled pull-up/pull-down/none circuit *if*
* Your FPGA/CPLD has a programmable output drive strength down to a low current
* You and your FPGA/CPLD can waste extra I/O current
For example, the Xilinx Spartan-3 pins can be programmed with a drive current down to 2mA. I think other devices go down to a lot lower but that's only from memory...
You can then do this in VHDL for your INPUT pin function:
Declare the pin in your entity as: iopin : inout std_logic;
iopin_in <= iopin;
iopin <= '1' when (iopin_pu = '1') else '0' when (iopin_pd = '1') else 'Z';
This is more an example of "what you can do" rather than "what's best for you to do" You have to weigh it all up, really.