[SOLVED] FPGA coding style behavioral vs structural modeling

Code VHDL - [expand]
1
2
3
if (rising_edge (ISA_CLK)) then
 
                        if (ISA_IOW = '0' and ISA_IOR = '1') then -- Write is enabled

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found
   that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock
   IOB component <ISA_CLK> is placed at site <P1>. The corresponding BUFG
   component <ISA_CLK_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is
   only a select set of IOBs that can use the fast path to the Clocker buffer,
   and they are not being used. You may want to analyze why this problem exists
   and correct it. If this sub optimal condition is acceptable for this design,
   you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
   this message to a WARNING and allow your design to continue. However, the use
   of this override is highly discouraged as it may lead to very poor timing
   results. It is recommended that this error condition be corrected in the
   design. A list of all the COMP.PINs used in this clock placement rule is
   listed below. These examples can be used directly in the .ucf file to
   override this clock rule.
   < NET "ISA_CLK" CLOCK_DEDICATED_ROUTE = FALSE; >

Code VHDL - [expand]
1
NET "ISA_CLK" CLOCK_DEDICATED_ROUTE = FALSE;

Code VHDL - [expand]
1
2
3
4
5
6
7
if (ISA_ABUS_IN = X"0500")
 
-----------
-----------
elsif (ISA_ABUS_IN = X"0501")
 
--- ETC

Code VHDL - [expand]
1
constant ADDRESS1 : std_logic_vector(15 downto 0) := X"0500";