FPGA Clock rise, fall time

[ku637]

Hello,

I'm looking at an FPGA design, whose clock (differential) data sheet specification (Table 54 ) has mentioned rise / fall time typical value as 200ps. ( only typical value is available)

The design is using a crystal clock source ~120MHz ( single ended) and use a Differential driver whose output specification says rise/fall time spec as Min:200ps, Typ: 500ps and Max:1ns

I'm doubtful as why the FPGA specification doesn't state maximum spec for rise time in this case or is it just like higher values of rise time is acceptable.

Will this be a problem in this case if the FPGA max rise/fall spec is <1ns. Any thoughts?

 

[barry]

I think this is a question for Xilinx. Usually there's a maximum rise time spec for input clocks, "typical" is a useless spec here.

 

[FvM]

120 MHz clock is well with 1 ns risetime.

 

[barry]

120 MHz clock is well with 1 ns risetime.

Frequency had nothing to do with rise time. A 120Mhz triangle wave has a risetime of about 4ns.

 

[KlausST]

Hi,

Frequency had nothing to do with rise time. A 120MHz triangle wave has a risetime of about 4ns.

Aren't both statements contradicting?
When a 120MHz triangle has a risetime of about 4ns, then
- in my eyes - a 60MHz triangle has a risetime of about 8ns,
thus the second statement says that "frequency has influence on risetime".

Where am I wrong?

Klaus

 

[dick_freebird]

Perhaps he meant to say that 1ns rise / fall won't
unduly compromise the "squareness" of the 8ns-period
(120MHz) clock. Rise and fall have to leave an "open
eye" region. Leisurely risetimes allow more transformation
of voltage noise to jitter, and can allow things like local
oscillation (via supply / ground loop) in the input buffer
so you'd like to have a max rise/fall time spec that
ensures these things don't happen, or have acceptable
error contribution.

 

[barry]

Hi,

Aren't both statements contradicting?
When a 120MHz triangle has a risetime of about 4ns, then
- in my eyes - a 60MHz triangle has a risetime of about 8ns,
thus the second statement says that "frequency has influence on risetime".

Where am I

Hi,

Aren't both statements contradicting?
When a 120MHz triangle has a risetime of about 4ns, then
- in my eyes - a 60MHz triangle has a risetime of about 8ns,
thus the second statement says that "frequency has influence on risetime".

Where am I wrong?

Klaus

Hi,

Aren't both statements contradicting?
When a 120MHz triangle has a risetime of about 4ns, then
- in my eyes - a 60MHz triangle has a risetime of about 8ns,
thus the second statement says that "frequency has influence on risetime".

Where am I wrong?

Klaus

An ideal 120MHz square wave has a rise time of zero. A 120 MHz trapezoidal wave can have a rise time anywhere between 0 and 4ns. A sawtooth can have a risetime of 8ns. Obviously, the rise time can't exceed 1/4 the period, but that's the only relationship between frequency and rise time.

 

[KlausST]

Hi,

An ideal 120MHz square wave has a rise time of zero. A 120 MHz trapezoidal wave can have a rise time anywhere between 0 and 4ns. A sawtooth can have a risetime of 8ns.

This makes sense.
So the "limit" for a symmetric signal with constat rise rate is a "triangle shape" with "4ns rise time for 120MHz" as you said.

Obviously, the rise time can't exceed 1/4 the period, but that's the only relationship between frequency and rise time.

You say "1/4 the period". This is new information. For 120MHz period time is about 8ns, so 1/4 is about 2ns.
I guess:
* 1/4 rise time
* 1/4 HIGH
* 1/4 fall time
* 1/4 LOW
..for a nicely shaped symmetric trapezoidal signal. I agree.

Klaus

 

[FvM]

Frequency had nothing to do with rise time. A 120Mhz triangle wave has a risetime of about 4ns.

You are answering a different question. The discussion is about real digital clock signals, not signal theory. Therefore I was telling the OP that a 120 MHz FPGA clock with 1 ns rise time is well in the range of aceptable parameters.

 

[barry]

You are answering a different question. The discussion is about real digital clock signals, not signal theory. Therefore I was telling the OP that a 120 MHz FPGA clock with 1 ns rise time is well in the range of aceptable parameters.

Since when is a "real digital signal", as you call it, defined to have 1ns rise time? A real digital signal can a much slower rise time depending on driving circuit, impedance mismatch, loading and so on.

 

[FvM]

A real digital signal can a much slower rise time depending on driving circuit, impedance mismatch, loading and so on.

Yes, we have minimal, typical and maximal rise time of a driver under specified load condition. On the receiver side we are looking at maximal acceptable rise time. That's what the OP is specifically asking for, because it's not specified in the data sheet. Respectively I was talking about this number, actual rise time at the FPGA clock input.

I assume that the proposed trapezoidal clock with 2 ns rise time would still work for the application, but probably involve increased jitter as explained by dick_freebird.