FPGA build with makefiles. The exported variable problem

[wtr]

Hello all,

I am aware that makefiles commands run in separate shells. However is it possible to get an exported variables into my next make target?

#Makefile
#somefile.mk will set $LOG_DIR & $SCRIPT_DIR
include somefile.mk

test:  
   export LOG_DIR=$(LOG_DIR); \
   .  $(SCRIPT_DIR)/set_env_var.sh

test2: test
   export LOG_DIR=$(LOG_DIR); \
   . $(SCRIPT_DIR)/write_variables.sh

Where set_env_var.sh does

XXXXXVARIABLE=somevalue            
export XXXXXVARIABLE               
set > $LOG_DIR/variables_out1.log

Where write_variables.sh does

YYYYYYVARIABLE=somevalue
export YYYYYYVARIABLE
set > $LOG_DIR/variables_out2.log

Basically want I'm trying to do is populate the current shell with a set of environment variables, that waterfall from one make target to the next. Such that variables_out2.log has YYYYYYVARIABLE AND XXXXXVARIABLE

Eventually the finally call will be a tcl script which will utilise the ::env(WHATEVER_VARIABLE) for the build of the FPGA.