mauriziomontesi
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fpga advantage
Hello there. I have created and simulated a project (a simple counter) with Mentor Fpga Advantage with Precision synt. Now I have to generate a .jed file (programming file) for a xilinx CPLD (XPLA3). Please (I'm new in Fpga adv, but I must use it, I know quite well Xilinx ISE) could you indicate me the steps to follow to generate programming file??( I have the project, now what I have to do???)
Please Help me
Maurizio
Hello there. I have created and simulated a project (a simple counter) with Mentor Fpga Advantage with Precision synt. Now I have to generate a .jed file (programming file) for a xilinx CPLD (XPLA3). Please (I'm new in Fpga adv, but I must use it, I know quite well Xilinx ISE) could you indicate me the steps to follow to generate programming file??( I have the project, now what I have to do???)
Please Help me
Maurizio