Four interview questions about clock frequency! Please HELP me! Thank you a LOT!!

[honeybunny]

There are 4 interview questions about clock frequency. I am very confused about the positive edge and negative edge clock. I mean I understand how they work, but don't quite know how to apply the knowledge I know in the questions, pleae help me solve these three, especially give me some hints about HOW to start with these type of questions. Thank you in advance.

1.
There are 2 DFF in parallel, one clock of those two is positive edge triggered, the other is negative edge triggered. Their outputs go into a NAND2 gate. The output of the NAND2 goes back to the inputs of both DFF. What is the relationship of the NAND2 output's frequency and the clock frequency of the two DFF?

Question 2-4 see the attached pictures.

2.
3.
4.

 

[ebclr]

Circuit 1 Isn't nand gate based is a xor gate that work as a controled inverter, The means that data in on flip flop 2 is function off clock / 2 and the xor feedeback, very interisting circuit

 

[honeybunny]

Circuit 1 Isn't nand gate based is a xor gate that work as a controled inverter, The means that data in on flip flop 2 is function off clock / 2 and the xor feedeback, very interisting circuit

You mean the first question? But the questions indicates it's a nand...not xor...

 

[sureshaa]

For question no 2: 1/4 th Clk freq with 25% Duty cycle.

 

[honeybunny]

For question no 2: 1/4 th Clk freq with 25% Duty cycle.

Thank you for your answer! I can figure out it's 1/4 clk freq, but how to get the duty cycle? And it seems the answer is with 50% duty cycle...(I am not sure whether this answer is right...it is given in that document I found) Will you tell me how you got the 25% duty cycle? THANK YOU VERY MUCH!

 

[Prashanthanilm]

Can you explain it how?

It will help me and other folks also.

 

[morris_mano]

For question no 2: 1/4 th Clk freq with 50% Duty cycle.

Qa Qb   Q`a  Q`b
0   0    1     1
1   1    0     1
0   1    1     0
1   0    0     0
0   0      --repeat--

Q`b is the final output, state changes every posedge of clock.

Hope this helps.

 

[qieda]

Hi,

for question 1.

the output of one FF is constant high, the other FF is toggling with clk/2 frequency.


for question 4.

assuming the inverter gives you an delay
F1 is AND or OR
F2 is XOR


regards

 

[Sk Hr]

Hi,

For question 1.

As my analysis. I got both flip flop produces output high for three input clock cycle and low for one input clock cycle.

Flip Flop one starts producing at pos edge and other at neg edge and continues.

NAND gate output is high for one full input clock period and is low for half input clock period.(looks like divided by two with 75% duty cycle)

Please explain if I'm wrong. If anybody know the answer please can you post waveform diagram here. If it is hand written also no prob.

It may help others also. Thank you in advance

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Hi,

Question number 4.

Take 2:1 mux short its both input terminals and connect to IN and connect its select input to Negated IN.

so by this we can get same wave form as input, same frequency and duty cycle.