mmrakshith
Newbie
I am doing an equivalence check between RTL and the netlist generated by Fusion Compiler (FC).
I have a set of 7 SVFs generated during different stages of compile in FC.
The SVF processing doesn't cross 50%, I tried to run by increasing the timeout, including more cores, more RAM, but nothing worked.
Supposing there are loops in the design, I could report it and get to know about it; but now I'm not able to enter the fm_shell prompt after the SVF processing itself and no way to save the session. Even if I did so, as the matching phase is not complete, the tool is not able to report any loops.
I also tried to interrupt the process so that if the tool is stuck resolving one loop, it could move on to the next one atleast, but its causing the tool to terminate.
The only info the tool is showing now is the warning FM-348. I'm not sure if this is the reason for the failure.
PS : Its not exactly a Formality failure as the matching itself is not complete.
Appreciate any inputs on this.
Thank you
I have a set of 7 SVFs generated during different stages of compile in FC.
The SVF processing doesn't cross 50%, I tried to run by increasing the timeout, including more cores, more RAM, but nothing worked.
Supposing there are loops in the design, I could report it and get to know about it; but now I'm not able to enter the fm_shell prompt after the SVF processing itself and no way to save the session. Even if I did so, as the matching phase is not complete, the tool is not able to report any loops.
I also tried to interrupt the process so that if the tool is stuck resolving one loop, it could move on to the next one atleast, but its causing the tool to terminate.
The only info the tool is showing now is the warning FM-348. I'm not sure if this is the reason for the failure.
PS : Its not exactly a Formality failure as the matching itself is not complete.
Appreciate any inputs on this.
Thank you