Formal verfication of DFT between placed netlist and synthesis netlist

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owen_li

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Hi.
As we know, in placement stage, PR tool will implement scan reorder on the design.
So, I want to know how to do DFT formal verfication between placed netlist and synthesis netlist.
coz, the shift path has been changed after placement, comparing to the synthesize netlist, how the formal
tool can pass this formal verfication.

Thanks!
 

scan_chain_reordering will not create any issue as such (during PnR).

Even though there will be change in flops in scan chain - however 1st flop & last from from that chain will be intact. so it will not create any issue in Formality.
 

owen_li, as you mentionned the placer could change the flops order along the scan chains, and so conformal tool could not formaly made a equivalency between the two netlists as the pin SI is not driven by the same SO pins.

You need to force scan shift signal to inactive, and the LEC tool will not check the SO->SI pins connections.

The same issue appears when you want to LEC between the netlist before scan insertion and after scan insertion.

To check if the scan chains are unbroken, using this netlist in an ATPG tool could confirm the stuck coverage if it is equivalent as you have obtained with the netlist after scan insertion.
 

But rca -
Do you thing in PnR during scan_chain_reordering - if the intermediate chain gets reordered, but 1st & last flop is intact - in that case Formality/LEC will fail??
 


Thanks for your reply, rca.
Do you mean ATPG simulation is the only way to check whether the scan structure is corrupted by PNR tools ?
Another case is about the maximum scan register number in a signle scan chain.
Is it the ATPG simulation only way to guarantee it after PNR implementation ?

Thanks!
 

I never indicate the ATPG simulation, but the using the ATPG tool to generate the patterns. If you are able the patterns, that means the scan chains are correctly implemented.
I am care of the maximum scan register number in a single scan chain only if you are limited by the tester.
PnR tool could only swap element from chain to another chain with respecting the lenght.

- - - Updated - - -

vcnvcc said:
But rca -
Do you thing in PnR during scan_chain_reordering - if the intermediate chain gets reordered, but 1st & last flop is intact - in that case Formality/LEC will fail??
Click to expand...

Yes, if the flop inside the scan chains are swapped, that means between two netlist the driven of the SI pin is not the same SO pin, so LEC will failed.
And for the 1st and last flop could be changed as well, and LEC will failed as well.
 


But rca - IMHO there is difference between functionality & test.

All we are talking about is related to scan (test); if I say those scan inputs are zero in Formality/LEC; in that case i dont think there should be any issue. All we have to run is ATPG simulation to verify its correctness.

Do you agree with that? if No, kindly share your inputs... Thanks.
 

The only way to pass a lec between these two netlists is to force the capture mode on the SE pin ('0'=functional mode). The test mode will be confirm if you are able to generate the stuck pattern with an ATPG tool.
The scan input could share a functional input, and so you could not force to '0' or '1'.
 

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