[SOLVED] Force logic selection during synthesis

Status
Not open for further replies.
K

keyboardcowboy

Member level 3
Joined
Mar 4, 2010
Messages
55
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,715
Is it possible to tag some logic in a Verilog design and have design compiler implement it using a specific logic structure?. For example if I have combinational logic in a always(*) block and I want to have it synthesized using only NAND, NOR, and INVERTERS how can I do that?. Ordinarily it uses a cell which is a combination of NOR and OR gates
 

Sort by date Sort by votes
Not sure why on earth you’d WANT to do that, but in VHDL you can instantiate primitives. I assume you can do something similar in verilog, along with some KEEP directives. But, really, why?
 

Upvote 0 Downvote
I know about logic primitives, but I want the synthesizer to use specific primitives (NAND, NOR, INV) for specific part of RTL. This is for some experiments I want to do
 

Upvote 0 Downvote
set_target_library_subset
Restricts the optimization of a block to a subset of the target
libraries.

-use lib_cells
Specifies library cells that can be used for optimization within
the block. This is in addition to the libraries listed in the
library_file_name_list argument.

set_libcell_subset
Restricts the optimization of sequential cells and instantiated
combinational cells to a family of target libraries.
 
Upvote 0 Downvote
In Cadence you use the set_dont_use command and you specify which gates it is allowed to use. If it is only in one block, you might have to tell it to set_dont_use, select the subcell, synthesize that only, set_dont_touch or set_size_only on it and then do the rest.
 
Upvote 0 Downvote
Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…