Hi VhdlExperts,
I would like to understand about how the timing is decided.
For example if i have a for loop inside a process which runs on every rising edge of the clock signal, Is it guaranteed that the for loop will complete within one clock cycle.
eg:
test: process(clk)
begin
if(clk ='1' and clk'event) then
for i in 0 to 100 loop
--- do somematrix multiplication.
end loop;
for i in 0 to 100 loop
--- do somematrix addition.
end loop;
end if;
end process;
Is the forloop guaranteed to complete within 1 clk cycle. Please explain.
Thanks.