[SOLVED] for loop in synthesizable rtl

[fragnen]

Using for loop with an integer i defined as the loop variable index, a synthesizable rtl can be coded.
Using for loop with genvar i declared as the loop index variable a synthesizable rtl can be coded.

Where is the difference in using a for loop with an integer i declared versus using a for loop with generate statement by declaring i as genvar in coding a synthesizable rtl?

 

[FvM]

They are used in different places of a Verilog program. For loop is a sequential statement, generate loop is a module item.

 

[fragnen]

A for loop can be used inside a module while writing a rtl. Then a for loop is also a module item. Why is then generate loop is only a module item and for loop is not?

What do you mean by a sequential statement when you state for loop is a sequential statement? A for loop can be also used in a always block where the always block are level sensitive to variables and the always block is for realizing a combinational logic.

 

[dave_59]

Realize that Verilog is used for both simulation and synthesis. A procedural-for loop gets executed at run time, and the bounds of the loop can be determined at run time. A generate-for loop requires that its bounds be determined at compile time.

Most RTL synthesis tools place restrictions on the bounds a procedural-for loop to be fixed at compile time as well, although some advanced tools only place a restriction on the maximin iterations.

 

[FvM]

Module item and sequential statement are well defined terms in the LRM.

Module items are placed the outer module level, not inside blocks, e.g. always blocks.

Sequential blocks are characterized by the ordered "execution" of statements, also combinational always blocks belong to it.

 

[fragnen]

Module item and sequential statement are well defined terms in the LRM.

Module items are placed the outer module level, not inside blocks, e.g. always blocks.

Sequential blocks are characterized by the ordered "execution" of statements, also combinational always blocks belong to it.

Seems generate for loop can be used in looping module instances, looping assign statements, looping inputs and outputs of a module. Is there any other place where the generate for lop can be used? Can for loop be also used in looping module instances, looping assign statements, looping inputs and outputs of a module?

Seems for loop can be used inside sequential statements like if-else, case, while loop, for loop, forever loop, repeat while these sequential statements are inside initial block, always block, task, function. Is this correct? Can generate loop be used in these scenarios?

 

[fragnen]

FvM

Can you please reply on the above queries in post#6?

 

[FvM]

It's all being said.

 

[fragnen]

FvM

Is post#6 also applies similarly as difference between generate case and normal case, generate if-else and normal if-else?

 

[D.A.(Tony)Stewart]

Using a generate with for loop in verilog

I'm trying to understand why we use generate in verilog along with a for loop. Using a generate and for loop together: reg [3:0] temp; genvar i; generate for (i = 0; i < 3 ; i = i + 1) begin: ...

stackoverflow.com

Verilog for loop - genvar vs int

When creating logic using a for loop, Verilog requires the loop index to be declared. I've seen examples where it's done with either "int" or "genvar" keywords. For example: // ...

electronics.stackexchange.com