"for loop" in FPGA

[Shoaib]

how can i use for loop on fpga. i need an optimized one.


________________
ShOaiB

 

[irum4]

for I in LOWER_LIMIT to UPPER_LIMIT loop
<some operators>
end loop;

 

[Shoaib]

what im looking for is "Synthesizable code"

 

[the_penetrator]

use generate statement in VHDL

it will create an array of elements as described in for...generate loop body

the C-like for-statement is not meant to be synthesizable

Cheers

the_penetrator_in_extremis©

 

[ZeleC]

LABEL:
for I in <lower_limit> to <upper_limit> loop
<statement>
end loop;
-- example:
--for I in 1 to 10 loop
-- I_SQR(I) := I * I;
--end loop;

 

[FNK]

I guess the poster is trying to do a number of sequential operations iteratively. A simple for loop as described above is useless in such a case, since all the operations are performed concurrently in HDLs. Use State Machines for such a case.

 

[ydao]

firstly, I must say, "for loop" is not for fpga directly, it's for the synthesis tools actually. It's just a combintional logic statement. the synthesis tools will calculte the logic equation's result and map it to gates!
look up in the synthesis software's manual.

 

[delay]

I don't understand the question. A FOR loop itself is not synthesizable.
Synthesizes means hardware translation. Hardware can result using some other statements with the FOR loop such as GENERATE. You need FOR in conjunction with other statements/function to develop a synthesized circuit.

delay (delayed by technology)

 

[neocool]

LABEL:
for I in <lower_limit> to <upper_limit> loop
<statement>
end loop;
-- example:
--for I in 1 to 10 loop
-- I_SQR(I) := I * I;
--end loop;

Does this also mean that I_SQR is a variable array?

And if you change it to :

   for I in 1 to 10 loop
     I_SQR(I) := I * I;
     I_SQR(I) := I_SQR(I) * I;
   end loop;

whould this code be still concurrent? Or would it produce an array of qubes of I?

 

[edavio]

suggest not to use loop in RTL code. It is hard to maintenance and understand. especially, synthesizor doesn't support loop state like that:



for I in "start-point" to "variable" loop
...
...
...
end loop

 

[ashishjindal76]

which hdl u r using for ur coding u fpga?

ashish

 

[Big Boy]

You need to use finite-state-machine (FSM).

You could also use a simple counter, incremented at each clock cycle.

 

[bibo1978]

A for loop can be synthesized if and only if its parameters are Constants, else it can't be synthesized, you can instead use an FSM, which of course will introduce a delay but you may pipeline the design, or else you may use an asynchronous FSM which is highly indesirable in FPGA designs mainly because the routing delays are not predictable, so an FSM and a pipeline can do what ever you want do.

thats all folks

 

[Aser]

Loops are synthesable
if constraints are static variables
and functions in the loop are synthesable,
and the synthesized netlist fit the FPGA resources.
Each iteration is mapped in its own resource.
That means that the loop is fully unrolled and than synthesized.
Therefore the loop I from 1 to 100
with the body X*Y gives 100 parallel multipliers.
Sometimes loops are very useful.
For example searching in the loop for the leading 1 in the vector
gives exellent parity check unit.

 

[Zerox100]

You can use FOR in HDL at any target level (Fpga, Asic). But you have to not do somethings.
1- Don't use break or exit in for.
2- Don't use variable length loop.
3- Don't use complex loops. for example "for ( if () . if () )". (it's always not good solution but sometimes synthesizable).
4- Try to use "generate" statements instead of "for loop".