for loop help in vhdl.....

[ramz]

for loop in vhdl

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity control_path_new_ver is

Port ( clk : in std_logic;
rst : in std_logic;
outp : out std_logic
);

end control_path_new_ver;

architecture Behavioral of control_path_new_ver is
signal count : std_logic_vector(2 downto 0) := "000";
--signal count : std_logic_vector(2 downto 0) := "000";

begin
process(rst)
begin
if ( rising_edge(clk)) then
--variable i : std_logic_vector(2 downto 0) := "000";

if(rst = '1') then

outp <= '0';

else

for i in 0 to 3 loop

if( i = 0 ) then
outp <= '1';
count <= "001";

elsif (i = 1) then
outp <='0';
count <= "010";

elsif (i = 2) then
outp <= '1';
count <= "011";

else
outp <= '1';
count <= "100";

end if;

end loop;

end if;

end if;

end process;


end Behavioral;


can i use the increated value of i in the loop in if statement for performing comparision.. i also need how many clocks r taken to have loop completed

 

[Mad I.D.]

for loop vhdl

for loop in VHDL is completed in zero time (not delta).
Look for some vhdl manual if you don't understand.

You can use temp. variable 'i' like that but I don't really understand why would you like to do that ?

There are much simpler ways to describe the circuit you want, just ask. First tell me what exactly should the circuit do

 

[ramz]

for in vhdl

actually i want to know a for loop works...
when i wrote a test bench.. the simulation results shown me only the last incremented value of for loop..
actually for any loop say i=0 to 5.. how many clock cycles are requied to perform this

Added after 2 minutes:

also i would like to know....

when loop starts.. say i=0 , i want to use this value for comparision in if statement..
eg : if(i=0) then do this...

elsif (i=1) do this.. and so on

 

[Mad I.D.]

loop in vhdl

when i wrote a test bench.. the simulation results shown me only the last incremented value of for loop..

Hehe. Well of course ! for loop is a sequential assignment statement and it is completed in ZERO TIME. There are no clock cycles needed to complete the loop.
You can only see the end result. Think this as a normal programming language as C, with an exception this loop finishes instantly.

One other thing, process in executed in delta simulation time (default is 0 ns). for loop in executed in no time at all (not even delta which can be 0ns).

Look for a definition of a process in VHDL and sequential statements

 

[FvM]

for i=0 loop vhdl

Use a counter, if you intend a clocked state machine.

signal counter: unsigned (1 donwto 0);
...
if(rst = '1') then 
counter <= "00"; 
else
counter <= counter + 1;
if counter = 0 then 
...

 

[honeyleabe]

vhdl see variable in for loop simulation

i have this ask too.
i want to output a array 12345 and loop it.
how can i do it?
thanks

 

[vipinlal]

There is a big problem with for loop's.The thing is that they cant be done with a clock.For doing clocked operations in for loop we have to use cascaded if statements.See more at this link:
https://vhdlguru.blogspot.com/2010/03/how-to-do-clocked-for-loop.html

 

[FvM]

There is a big problem with for loop's

I don't see a problem with for loops. There is a problem with HDL programmers that start writing code without learning the
language or at least consulting a handbook from time to time.

 

[vipinlal]

@FvM : ok.. i agree with you.Is there any way to do a for loop in which the loop indexes increment only during positive or negative edges of clock cycle.I couldn't find any method online.pls help.

 

[FvM]

increment only during positive or negative edges

If you mean one increment for each clock cycle, clearly no. That's not the purpose of a VHDL (Verilog is basically the same)
iteration scheme. It specifies an action, that has to be performed for each index value in parallel. If the block containing
the for loop is controlled by an edge sensitive condition, the complete loop is executed at each clock cycle. The sequential
aspect of the iteration matters if it uses variables, so the result of preceedings iteration steps must be considered in the following.

Except for the special effects with variables, you can regard a for loop as the sequential code variant of a generate statement.

Generally, I suggest a VHDL text book or a good VHDL compiler handbook, e.g. the Synopsis manual:

 

[suleman]

Hi
I am having a little trouble with loops as well.\

I am interested in getting samples of a an arbitrary waveform from an external signal using a simple D flip flop. (mind it that the incoming waveform signal is unknown)

So what I am doing is, that I need to sample the incoming waveform for only one second and see what is that shape of the incoming signal during this one second period. I have the internal clock running at 50MHz on the FPGA board and I am using this clock to sample the incoming signal pulses. So whenever the clock is high, I simple sample the input waveform to output. But I want to have some control over the timing. I mean I want to do this sampling only for one second.

After I have sampled the incoming signal for one second, i will repeat the same procedure for next one second and so on and so forth.

I am having a trouble coding it in VHDL. Can someone help me on this please?