chris_li
Member level 2
Hi Guys,
I got a design(without PLL), which includes a "clock generator" driving the whole chip. The "clock generator" has one clock root and generate many clocks by using different logic circuits, especially there is no divider circuit! In other words, only logic gates in this subblock, but the combinational circuits look not simple!!!
As above, I wonder whether I should sort out ALL the gates on each clock distributed path from root to generated clock and declare them not as clock sink when CTS?
Thanks.
I got a design(without PLL), which includes a "clock generator" driving the whole chip. The "clock generator" has one clock root and generate many clocks by using different logic circuits, especially there is no divider circuit! In other words, only logic gates in this subblock, but the combinational circuits look not simple!!!
As above, I wonder whether I should sort out ALL the gates on each clock distributed path from root to generated clock and declare them not as clock sink when CTS?
Thanks.