folded cascode biasing

[deep_sea]

Hello fellows,
I am wondering how to generate the biasing voltages of folded cascode (VG3,VG5,VG7,VG9)?
How to determine which voltage levels should be there and what circuit to generate?
I have tried current mirror for PMOS part but how to bias NMOS part?
Thanks in advance,

 

[Dominik Przyborowski]

There is a number of similar threads here in this forum already.
One hint, transistors are biased by current, not voltage.

 

[deep_sea]

Thanks for your reply. I know that transistors are biased by current. What I ask is do I need two current mirrors? Let us talk in more details.
Assume pmos input pair biased by a tail wide swing cascode.
Now the drain of this pair is connected to a drain of an nmos (M4). M4 should be biased by (2*IB) for example. Should I use another wide swing current mirror to bias it? In this case, the cascode voltage should be the voltage of the wide swing cascode.
What about the load part? Should I use a third current mirror to bias the PMOS cascode load?

 

[sutapanaki]

You can have a look at this thread

https://www.edaboard.com/threads/biasing-of-wide-swing-current-mirror.382799/#post-1658840

 

[deep_sea]

Thanks sutapanaki for ypur reply.
I have attached a possible biasing scheme for single ended output folded cascode.
The wide swing cascode current mirror is used to bias the tail current source with 2*Ib. The same current mirror is used to bias the mirror load with Ib through VB3 and VB4.
For the NMOS side, M2a,b were guaranteed to be in saturation by connecting its gate to the drain of M3a,b. For M3a,b to be in saturation, a resistor is used to have a certain VGD below Vth. A similar resistor is added to the output side for balance. It might be not necessary if balance is not required.
There are common mode feedback circuits that could be used also for biasing, in particular in fully differential OTA.

 

[sutapanaki]

You don't need common-mode feedback in the case of a single ended amplifier. Connecting the gates of M2a,b to the drains of M3a,b does not guarantee the saturation operation of those transistors. What guarantees it is the gate voltage and the Vov of M3a,3b.
Where did you copy this description from?

 

[deep_sea]

I did not copy it. I created it.
I have said exactly what you say. The Vov over the resistor from M3 drain to gate is set by the resistor value lower than the threshold voltage to guarantee saturation operation.

 

[sutapanaki]

I'm sorry, I probably misunderstood what you've written. It looked to me that when you mentioned the resistor you were describing the operation of M3a.b. An what I was saying was that M2a,b were not guaranteed to be in saturation by M3a,b, being in saturation.