folded cascode biasing ........??

Status
Not open for further replies.
A

ASHUTOSH RANE

Member level 2
Joined
Aug 7, 2009
Messages
49
Helped
2
Reputation
4
Reaction score
1
Trophy points
1,288
Location
KOZICODE
Activity points
1,589
HELLO GUYS
PLEASE TELL ME HOW TO GENERATE BIAS FOR Vb1 and Vb2

i have attached pic
 

Hi, ASHUTOSH RANE
Two examples of biasing nmos are depicted on the picture below:

The first way (left current source on the picture ) is the most simple way if you have enough voltage headroom. And the second way (right current source on the picture) lets you increase the dynamic output voltage range at the cost of drop in output resistance.The width of transistor N11 is 9 times less than that of other transistors in this example. You can vary this parameter and see how the picture of output resistance vs. output voltage changes and choose appropriate value.
Small signal output resistances are on the figure below:

Regards, pavel.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…