Hi,
THe above shown schematic is of NMOS input folded cascode amplifer, Lets say of we add PMOS input also in this schematic so that we can have HIGH ICMR. Then what is the role of M7 M8 M5 and M6 tranistors in both the cases when input CM if Higher and when input CM is Lower. I want to know which parameter it will effect and how
M7/M8 and M6/M5 are the "guards", "common-gate
amplifiers" making the M10/M9, M4/M3 current sources
into higher-Rout.
If you add a P stage then you'd connect its "horns" to
M3/M4 drain, appropriately for the same gain-direction
as the NMOS front end produces. The present schematic
may need you to size up M3/M4 to add the current that
the new PMOS front pair would try to take away, at null.