Flop to Integrated clock gater timing issues

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srp8514

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Hello,

If you have a flop that drivers another flop and a integrated clock gater (ICG) then which path will be critical ?
The Flop to ICG or Flop to flop ?

This was an interview question.

Thanks
srp8514
 

Critical path is the timing path with maximum delay that limits the maximum frequency of the design.
considering the delay between the Flop->ICG and Flop-> Flop is same, the critical path would be Flop->Flop because ICG is latch based design, where time borrowing is possible.
 
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