Flop to Integrated clock gater timing issues

[srp8514]

Hello,

If you have a flop that drivers another flop and a integrated clock gater (ICG) then which path will be critical ?
The Flop to ICG or Flop to flop ?

This was an interview question.

Thanks
srp8514

 

[morris_mano]

Critical path is the timing path with maximum delay that limits the maximum frequency of the design.
considering the delay between the Flop->ICG and Flop-> Flop is same, the critical path would be Flop->Flop because ICG is latch based design, where time borrowing is possible.