Floorplanning , Timing optimisation and Power optimisation methods in IC Compiler

[Sumit Apte]

Floorplanning , Timing optimisation and Power optimisation methods in ICC

Hi All,

I have recently joined a company for the post of Physical design engineer.

Can anyone please help me with best practices/methods/tips/tricks/commands/scripts anything that will explain
methods/steps for good floorplanning, timing optimisation and power optimisation.

It will be really helpful if senior designers on this forum could guide newbies like me.

Regards,
Sumit

 

[tpetar]

Did you try to get some nice literature for that first ? I want to say this is wide ranged question, better is to ask something more precisely.

 

[Sumit Apte]

Did you try to get some nice literature for that first ? I want to say this is wide ranged question, better is to ask something more precisely.

Hi,

Thank you very much for the reply.

Im searching for material,but whatever I have found so far is really basic one and nobody has listed commonly used commands or techniques.

Can you please list few methods or commands commonly used for timing optimisation in ICC ? It will be really helpful.

Regards,
Sumit

 

[Manochitra]

Hi,

For floorplaning tried to learn how to decide core width and height based on placement density...... learn power planning commands,and how to align pin location
For timing optimisation u have to come across these terms setup, hold, skew violations, slew ,arrival time,required time, fanout, slack..................... The above mentioned are some violations we come across during timing optimisation..... after that learn encounter tickle commands.... u can search them on encounter user guide and command reference ...

some of the commands used

placeDesign
report_timing
report_constraint -all_violators
clockDesign -genSpecOnly Clock.ctstch
timeDesign -preCTS
ckSynthesis
timeDesign -postCTS
specifyClockTree -clkfile Clock.ctstch

I have listed few commands based on timing and clk tree synthesis.. but there are plenty of them... so it is better to use command reference to find them.....

 

[Sumit Apte]

Hi Manochitra,

Thank you very much for the reply. I will go on and read about all those terms in detail
Also thanks for those commands...i will check for man pages of all those commands.

Can you give some info about timing optimisation using buffers ? and how to add them on time critical paths ?

Also if u have info tell me how to use preroute_focal_opt and focal_opt commands .

Regards,
Sumit

 

[Manochitra]

Hi Manochitra,

Thank you very much for the reply. I will go on and read about all those terms in detail
Also thanks for those commands...i will check for man pages of all those commands.

Can you give some info about timing optimisation using buffers ? and how to add them on time critical paths ?

Also if u have info tell me how to use preroute_focal_opt and focal_opt commands .

Regards,
Sumit

Hi...
steps to remove Setup violations:
=> upsizing the driver (ecochangecell -inst inst name -upsize)
=> Downsizing the receiver
=> buffer long wire (ecoAddRepeater -term inst name -cell cell name)
=> delete unnecessary buffers (ecoDeleteRepeater -inst inst name
=> late clocking EndFF
=> early clocking startFF
steps to remove Hold violations:
=> Downsize cell to increase the delay
=> Insert buffer
=> clksizing (upsize EndFF clock or Downsize StartFF clock path)

I have mentioned here about encounter tool commands.... There are many tool for synthesis and P&R............ we are using RC compiler for synthesis and for P&R(Placement and Routing) we are using cadence Soc Encounter ......
(Ex) Tool like encounter,synopsys,primetime,magma Talus are used for P&R...U have mentioned here as IC compiler...Normally compiler tools are used for synthesis...It is better to mention which tool u are using for P&R and collect the commands regarding to that tool.....

 

[lohi21]

Start with the tutorial, Some one in your company might have atteneded the IC compiler workshop. Go over the book and try to familirise the flow first. all PNR tool would differ while implemention. Which ever tool you have been assigned, start with workshop of that tool first, get familiarized with the flow.