Floor-Planning in ISE

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salma ali bakr

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ise logic lock

If you open the floor planning editor after P&R in ISE, you will see the synthesized design logic components are mapped randomly to the CLBs on the floor. I am sure there is a way to force the P&R tool to collect all design components in one area (so that all components are close to each other instead of being randomly located on the FPGA floor). I just forgot how to do that. Please let me know if you have any suggestions.

thanks in advance,
salma
 

floorplanner +ise

there is some tools you can used to do floorpaning in xilinx FPGA. you can use the Floorplanner or planAhead for your design floorplanning.

another alternative way is to assign area constraints to partition your design and spcify the placement of your design. details you can read up the constrains user guide.
 

Use logic-lock for xilinx devices. Just drag and place the logic into a particular location and then lock it.
 
someone helped me out in the xilinx forums

it can be solved by the "area_group" constraint
 

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