Float pkg is not working in VHDL

Soh_bhat said:

Hi,
Good day. I am trying to use float_pkg in VHDL, but it is throwing error " float_pkg is not compiled in ieee". I've tried ieee_proposed also but unfortunately it is giving the same error.
I tried using some fpu units from the internet but don't know how to use it in my code.
Can anyone help me with a glimpse of a code of how to use it?
Or, how can I use floating point do that the program is synthesized?
Actually i got the simulation using 'type' but while synthesizing it is not working.

Please help!

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Soh_bhat said:

Hi there, here's the code without float pkg.

Code:

Behavioural:
package pk5 is
 type T is range 0.0 to 50.0;
 type T1 is array (0 to 3) of T;
end pk5;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use work.pk5.all;

entity add is
   Port ( x : in T1 ;
          y : in T1;
          h : in T;
          x_o : out T1;
          y_o : out T1);
end add;

architecture Behavioral of add is

signal p, q : T1;

begin

process(x, y, h)
begin
p_o(0) <= x(_o0);
q_o(0) <= y_o(0);

addi: for i in 1 to 3 loop
p_o(i) <= p(i-1) + h;
q_o(i) <= q(i-1) - x(i-1);
end loop;
x_o <= p;
y_o <= q;
end process;
end Behavioural;

Test Bench:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use work.pk5.all;

entity add_TB is

end add_TB;

architecture Behavioral of add_TB is

component add is
Port ( x : in T1;
          y : in T1;
          h : in T;
          x_o : out T1;
          y_o : out T1);
end component;

signal x: T1;
signal y: T1;
signal h: T;
signal x_o: T1;
signal y_o: T1;

begin

uut: add port map (
x => x,
y => y,
h => h,
x_o => x_o,
y_o => y_o);

add_proc: process
begin
 x(0) <= 1.0;
   y(0) <= 10.0;
   h <= 0.1;
  wait for 5 ns;
 end process;

 end Behavioral;

Here, using type it is running the simulation but it is not synthesized. Whenever I am using ieee.float_pkg.all or ieee_proposed.float_pkg.all, it is giving a red mark over there and its not running. I dont know how to change the code to make it synthesized.
I also downloaded some fpu unit from freecores/fpu_double, but don't know how to use it using VHDL code.

Please help!

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