Flip-flop behavior on power loss.

[MrCravon]

I have a signal on the input of an IC that is held high by a pull-up resistor. The same signal is connected to the output of a D-flip flop. This enables me to Clock a 0-value on to the flip flop output and drive the signal in question low. Driving the signal in question low will result in VCC to the D flip-flop driving the signal to be cut off. My question is cutting the VCC of the D-flip-flop enough to stop it driving the output to 0 and effectively allowing the pull-up resistor to pull the signal back up?



The picture is just for illustrative purposes and not complete.

 

[Warpspeed]

Probably not...
There is a distinct possibility that the flip flop will be reverse powered through the pull up resistor even if you remove Vcc2.
A whole lot depends on the logic family of the flip flop, and what else is powered on Vcc2.
Its all a very bad idea.

Your best bet might be to place a low power mosfet between the flip flop and microcontroller.
When you kill Vcc2 the gate will have nothing to power it, and mosfet will remain off.
When the gate is high, it will pull the input to the microcontroller low.