Flip Flop based memory instead of RAM

entity memory is
generic 
(       	
  CELL_WIDTH : positive := 8 ;
  NUMBER_OF_CELLS : positive := 4 ;
  NUMBER_OF_WRITE_PORTS : positive := 1 ; 															
  NUMBER_OF_READ_PORTS : positive := 1 		
) ;													
port														
( 		
  CLOCK : in std_logic ;          								
  WRITE_REQUEST_VECTOR : in std_logic_vector ( NUMBER_OF_WRITE_PORTS - 1 downto 0 ) ;										
  READ_REQUEST_VECTOR : in std_logic_vector ( NUMBER_OF_READ_PORTS - 1 downto 0 ) ; 										
  WRITE_ADDRESS_ARRAY : in type_array_unsigned ( 0 to NUMBER_OF_WRITE_PORTS - 1 ) ( log_2_decimal ( NUMBER_OF_CELLS ) - 1 downto 0 ) ;				
  READ_ADDRESS_ARRAY : in	type_array_unsigned ( 0 to NUMBER_OF_READ_PORTS - 1 ) ( log_2_decimal ( NUMBER_OF_CELLS ) - 1 downto 0 ) ;	
  INPUT_DATA_ARRAY : in type_array_slv ( 0 to NUMBER_OF_WRITE_PORTS - 1 ) ( CELL_WIDTH - 1 downto 0 ) ;									
  OUTPUT_DATA_ARRAY : out type_array_slv ( 0 to NUMBER_OF_READ_PORTS - 1 ) ( CELL_WIDTH - 1 downto 0 ) 							
) ;             

end entity memory ;


architecture synthesizable_memory of memory is

type type_array_data_memory is array ( 0 to NUMBER_OF_CELLS - 1 ) of std_logic_vector ( CELL_WIDTH - 1 downto 0 ) ; 	
signal memory_matrix : type_array_data_memory ;																		
begin

  writing : process ( CLOCK ) is
  begin
    if rising_edge ( CLOCK ) then 
      for index in INPUT_DATA_ARRAY ' range
      loop
        if WRITE_REQUEST_VECTOR ( index ) = '1' and PORT_IN_SLV_ENABLE ( index ) = '1' then 
          memory_matrix ( to_integer ( WRITE_ADDRESS_ARRAY ( index ) ) ) <= INPUT_DATA_ARRAY ( index ) ;  	
        end if ;
      end loop ;	
    end if;	
  end process writing ;			
  
  reading : process ( CLOCK ) is
  begin
    if rising_edge ( CLOCK ) then 
      for index in OUTPUT_DATA_ARRAY ' range
      loop
        if READ_REQUEST_VECTOR ( index ) = '1' then
          OUTPUT_DATA_ARRAY ( index ) <=  memory_matrix ( to_integer ( ( READ_ADDRESS_ARRAY ( index ) ) ) ) ;	
        end if ;
      end loop ;	
    end if;	
  end process reading ;

end architecture synthesizable_memory ;