In my circuit, I have the frequency response shown below, as you can see at the area near to unity gain becoming horizontally flat. However, my phase margin measurement is good and it is 71 deg.
this flat region is some hoe I am not comfortable with it because always people talk about single pole LPF response as an ideal case,
I have done the pulse response, the peaking is reasonable as you see below
Show your schematics.
The flat region you mentioned is an LHP zero. You can see that by the increase in phase (and gain). If this is a two-stage miller compensated amplifier, it means that your zero is before the second pole. As you mentioned, this will affect your amplifier's settling behavior.
it is folded cascode class AB buffered opamp
I used the negative compensation attempting to increase the circuit gain bandwidth product (GBW), but only the unity gain frequency increase (UGB).
in my circuit I have now GBW = 150 MHz,
and for the UGBW = 250 MHz,
I think the GBW should be the important one right?
This paper presents and compares two CMOS (complementary metal oxide semiconductor) operational amplifier (op-amp) designs. Each op-amp is based on a two-stage rail-to-rail output where the first stage is a differential input with folded cascode and the second stage forms a class-AB amplifier...
You are probably not showing the resistors in series with the output stage miller capacitors (we can only guess). Cadence schematics are more helpful in this case. The whole freq. response will be important for the settling behavior, so if you want a single pole settling, you should have about -20dB/dec slope till you reach the 0dB point.