rahdirs
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For a single word programming,this is the command cycle to be followed:Saying the timing diagram in post #1 is a "4 cycle command" misses the point. Instead it shows different phases involved with programming:
Yes.So,for example the toggling of CE signal is only at the last two command cycles & the rest i can keep CE as '0' ?
Yes.
Additionally, in many cases, a CE change in the timing diagrams doesn't mean that CE must be actually operated. It only shows the required relation between CE and the second control signal, OE or WE.
Do you wait for finish of each write command before starting a new one?
Of course we don't know what you are exactly doing. How and when are you erasing the flash sector? Which value do you read from the other locations?
Looks like either the write or the read sequence isn't performed as intended (respectively required).
Did you check the design in a simulation?
Looks like either the write or the read sequence isn't performed as intended (respectively required).
Did you check the design in a simulation?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 when data_write_1_1 => USERFL_CEn1 <= '1'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; dsel <= x"1"; --- data = x"00AA" asel <= x"1"; --- address = x"0000555" msel <= '1'; writeo <= '0'; testo <= x"02"; b <= x"0000"; a <= x"0"; wait_cnt <= x"0000"; when data_write_1_2 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; writeo <= '1'; a <= a + '1'; testo <= x"03"; when data_write_1_3 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; if (b <= 8) then USERFL_WEn <= '0'; else USERFL_WEn <= '1'; end if; writeo <= '0'; a <= x"0"; testo <= x"04"; b <= b + '1'; when data_write_2_1 => USERFL_CEn1 <= '1'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; dsel <= x"2"; -- data = x"0055" asel <= x"2"; -- address = x"00002AA" msel <= '1'; writeo <= '0'; testo <= x"05"; b <= x"0000"; when data_write_2_2 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; writeo <= '1'; a <= a + '1'; testo <= x"06"; when data_write_2_3 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; if (b <= 8) then USERFL_WEn <= '0'; else USERFL_WEn <= '1'; end if; writeo <= '0'; a <= x"0"; testo <= x"07"; b <= b + '1'; when data_write_3_1 => USERFL_CEn1 <= '1'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; dsel <= x"3"; -- data = x"00A0"" asel <= x"1"; -- address = x"0000555" msel <= '1'; writeo <= '0'; testo <= x"08"; b <= x"0000"; when data_write_3_2 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; writeo <= '1'; a <= a + '1'; testo <= x"09"; when data_write_3_3 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; if (b <= 8) then USERFL_WEn <= '0'; else USERFL_WEn <= '1'; end if; writeo <= '0'; a <= x"0"; testo <= x"0A"; b <= b + '1'; when data_write_4_1 => -- dsel <= x"b"; -- data = to be Programmed data -- asel <= x"6"; -- address= Program address USERFL_CEn1 <= '1'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; dsel <= x"0"; asel <= x"0"; msel <= '1'; writeo <= '0'; testo <= x"0B"; b <= x"0000"; when data_write_4_2 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; USERFL_WEn <= '1'; if (a=2) then data_rd_en <= '1'; addr_cnt_en <= '1'; else data_rd_en <= '0'; addr_cnt_en <= '0'; end if; writeo <= '1'; a <= a + '1'; testo <= x"0C"; when data_write_4_3 => USERFL_CEn1 <= '0'; USERFL_OEn <= '1'; if (b <= 2) then USERFL_WEn <= '0'; else USERFL_WEn <= '1'; end if; writeo <= '0'; a <= x"0"; testo <= x"0D"; b <= b + '1'; -- if(b=1)then cnt_data <= cnt_data + '1'; addr_cnt <= addr_cnt +'1'; -- end if; when wait_state1 => testo <= x"FA"; wait_cnt <= wait_cnt + '1';
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 when data_write_1_1 => nextstate <= data_write_1_2; when data_write_1_2 => if (a = 5) then nextstate <= data_write_1_3; else nextstate <= data_write_1_2; end if; when data_write_1_3 => if (b = 10) then nextstate <= data_write_2_1; else nextstate <= data_write_1_3; end if; when data_write_2_1 => nextstate <= data_write_2_2; when data_write_2_2 => if (a = 5) then nextstate <= data_write_2_3; else nextstate <= data_write_2_2; end if; when data_write_2_3 => if (b = 10) then nextstate <= data_write_3_1; else nextstate <= data_write_2_3; end if; when data_write_3_1 => nextstate <= data_write_3_2; when data_write_3_2 => if (a = 5) then nextstate <= data_write_3_3; else nextstate <= data_write_3_2; end if; when data_write_3_3 => if (b = 10) then nextstate <= data_write_4_1; else nextstate <= data_write_3_3; end if; when data_write_4_1 => nextstate <= data_write_4_2; when data_write_4_2 => if (a = 5) then nextstate <= data_write_4_3; else nextstate <= data_write_4_2; end if; when data_write_4_3 => -- nextstate <= idle; if (b = 5) then if(addr_cnt >= sect_end_addr)then nextstate <= idle; else nextstate <= wait_state1; end if; else nextstate <= data_write_4_3; end if; when wait_state1 => if(wait_cnt>=10000)then if(USERFLASH_RYBY = '1') then -- nextstate <= data_write_1_1; nextstate <= idle; end if; else nextstate <= wait_state1; end if;
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