Having a FLASH fabric - Actel is inherently non-volatile while SRAM based FPGAs (Altera/Xilinx/Lattice) must load from every power-up from an external flash.
Both are programmed using a JTAG interface.
FLASH based FPGA's are much less power hungry. They also seem to have the benefit of requiring less power supplies (of different voltage level), so PCB integration should be easier.
They are however much smaller devices (logic wise) - Xilinx and Alera offer greater densities.
Also, I think the ACTEL design tools are much worse.
What's wrong with your spartan 3E ?
Also what do you mean that the ACTEL design tools are "much worse" ? Should I be expecting problems along the way?
I could work with thatThey use "Synopsys - Synplify" for synthesis wich is rather OK. But the place & route tool is made by Actel.
Compared to ISE it feels "low quality". More crashes, bugs , less intuitive and less user friendly.
With that said - I have to note that in the end it does work and will produce a functioning design. I've used Actel IGLOO nano and PROASIC 3 in high reliability projects.
The current version of Libero uses Synplify Pro, which does have some nice features of register balancing and schematic generation similar to ISE. I've noticed over the years that Synplify has lost ground to both Altera and Xilinx synthesis in terms of QoR. The Libero back end tools definitely feels low quality as in antiquated compared to the latest versions of ISE. Libero is more akin to Xilinx's Foundation series of tools back in the late 90s.They use "Synopsys - Synplify" for synthesis wich is rather OK. But the place & route tool is made by Actel.
Compared to ISE it feels "low quality". More crashes, bugs , less intuitive and less user friendly.
With that said - I have to note that in the end it does work and will produce a functioning design. I've used Actel IGLOO nano and PROASIC 3 in high reliability projects.
I'll be glad to help.do you mind if I contact you within the next few weeks if I needed more information?
The current version of Libero uses Synplify Pro, which does have some nice features of register balancing and schematic generation similar to ISE. I've noticed over the years that Synplify has lost ground to both Altera and Xilinx synthesis in terms of QoR. The Libero back end tools definitely feels low quality as in antiquated compared to the latest versions of ISE. Libero is more akin to Xilinx's Foundation series of tools back in the late 90s.
You should keep aware you will likely need to select a much larger part (based on number of logic elements) than what you would normally use for a Spartan 3E design as the building blocks (basic logic elements) in the Actel parts is unlike the Xilinx/Altera LUT/Register combination cell. You can easily eat up a large number of versatiles in the Actel architecture that would require only a small number of CLBs in a Xilinx part. For example we have a SPI slave which takes approximately 200 LUTs in a Virtex 6 part which after cutting out over half the programmable registers in the design took up 90%+ of a ProAsic3 nano 20K part. (YMMV)
Regards,
-alan
It may help if you describe the main elements in your design and estimated required I/Os.
Alan are you sure about this? because if you are that would mean to expect some problems along the way.
Why did you decide to use an FPGA ?
It seems like your project will be easier (and cheaper) to implement with a uC.
An ARM Cortex M3 like a hand for a glove...
When it says 7% - I think it means that the design stretches over that portion of the device. That doesn't necessarily mean that it can't take less space! The tool made no such effort, because it didn't have to.
To elaborate - think of the back row of a regular passenger car. I've seen once a group of 5 people cramp in that confined space. However, if you seat there by yourself and assume the most comfortable position with your legs stretched - you may well occupy more than a single seat!
Same thing with your ACTEL - the tool sees that your design is small and all alone. Therefore it makes no effort farther compacting it...
About the MCU option:
ARM is the most popular and scalable plattform to date.
Its tool support and vedors availability is simply incomparable to any other.
Also, upgrading in the future will be much easier.
By itself the Cortex M3 is a very capable device:
It's 32 bits, has hardware divide and multiple, low power and usually comes with a vast array of peripherials (the last has more to do with the vendor's implementation than with the actual ARM core).
The M3 has established itself as THE industry standard in the microcontroller market.
Simply put:
If I needed VERY low power consumption (the lowest possible) with low processing capabilities - I'd go with a Microchip PIC or TI MSP430.
If I needed VERY high processing capabilities at resonably low power I'd go for a TI or FREESCALE DSP.
From your description I conclude that your project falls under neigther of the above requirements. You need a microcontroller with analog capabilities, capable peripherals and all that at low power - Cortex M3 will fit that bill perfectly.
I suggest you look under the following vendors for the most suitable Cortex M3 for your application:
1. Cypress
2. ST
3. FREESCALE
Good luck
The results of that port were definitely surprising based on Actel's counting of "gates". Though after looking at Actel's logic element it's not surprising. There's not much logic in them to begin with.
I agree with shaiko you should probably consider a micro.
Hmmm, the block diagram shows a micro. ;-)
https://www.youtube.com/watch?v=rX3KKTl3zdQ
https://www.youtube.com/watch?v=7j1M_I3lG_0
I think you'll find this very interesting. I've never used this device in one my designs - so I'm no expert on it...but from what I can see, the capabilities seem to be tailored for your kind of project.
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