It depends on the application whether "offset is a problem".shown bellow has no offset voltage problem at all
I recommend to connect a fix 100R resistor between IN+ and GND,I would suggest a 10K resistor from VCC to the top end of a 100 Ohm potentiometer and a 10K resistor from the bottom end to VEE with the wiper going to the non-inverting (+) pin on U7.
Further, adding a trimming pot can actually make things worse due to the temperature coefficient of the pot.The reason why offset adjustment pins are rarely used with LT1028 is that offset and offset drift over temperature are already wafer trimmed during fabrication. The achievable improvement by additional in-circuit trimming isn't so large.
It is good to understand the cost of Vos trimming is effective and increases with the time required to laser trim. It is a fascinating process done on the wafer that looks like a (silent) "Star Wars battle" with sparks flying all over the wafer from a high-power laser being deflected with precision during the measurement.
I should have known better to limit the description of my observations to 40 yrs ago with thicker film devices being laser trimmed on ceramic at C-MAC in Sherbrooke.Properly done, laser trim creates no sparks. The thin film resistor
material (a few hundred angstroms of NiCr or SiCr) is ablated and
entrains to the glass layers above and below, without damage to
oxide. This is key to passing HiRel die visual inspections.
There's a lot of tweaky process stuff involved. The oxide under the
trim resistors must create positive interference (not negative) to
maximize heat in the film, not elsewhere. This is optically inspected
(a specific color indicates a specific wavelength, which should be
half of the IR laser head wavelength).
Test is even "tweakier". The time to trim is a die level cost adder,
sure, but there's huge sunk cost in getting to a test solution that
delivers the Vio, every time. From die level pattern seeking to sub-
micron laser-head stepping, with a subset of fine testing per, and
by the way control your power level so your kerf-adjacent heat
affected region stays minuscule (no annealing). This also wraps
back around to oxide tuning, any detuning affects more of the
close in material still connected across. This leads to design of
compound trim structures, where "links" handle most of the range
and a tab or top hat patch delivers the sub-sub-LSB precision
(other aspects of the process, determining the accuracy after
burnin and lifetest - either per-packaged-part, or as a step in
qualifying the test*process combo for production.
We used to have a special room on the test floor with 4 big LTX
test stations, just for the parts that needed this kind of thing.
They do like to eat, and so do the test engineers who have to
stand it up and keep it up.
Now the point about 1uV, 5uV op amps is worth a look if Vio is
what matters, and bandwidth & spurious noises don't. There
are many rail-rail, "zero offset" chop amps out there which, if
you can tolerate a low frequency post filter, could be just the
ticket. Many in the 5V range, but some up to 40V, out there.
The op amp market is sliced pretty thin along lines of detail
parameter care-abouts and shopping is an exercise in itself.
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