fixed burst in AXI

[abdelaali]

Hey all,
I'd like to know if data changes for a fixed burst in AXI in contrary of address ?
Any help will be much appreciated

 

[fragnen]

Fixed burst is for a fixed address for the entire data of AXI fixed burst.

 

[abdelaali]

Yes same address for entire burst. But can data change from one beat to another
exmaple
Fixed burst
Burst lengh 2
Data bus width 32
beat 1 : ABCD
beat 2 : 120F

 

[ads-ee]

The address sent is the starting address, the address is auto-incremented by the slave and the data transfer beats have whatever data the master wants to send.

This is all explained in the Amba AXI spec. You might want to go download it from the ARM website.

 

[TrickyDicky]

@ads-ee Your description is for when the AxBURST signal is set to INCR
if it is FIXED - then the address is fixed for every beat of the burst.

 

[fragnen]

Yes same address for entire burst. But can data change from one beat to another
exmaple
Fixed burst
Burst lengh 2
Data bus width 32
beat 1 : ABCD
beat 2 : 120F

Yes, data can change from one beat to another.

 

[dpaul]

@abdelaali ,
Yes data can change, and I did not find any exception to this inside the AMBA AXI spec.
Excerpt:

Burst type
The AXI protocol defines three burst types:

FIXED - In a fixed burst:
• The address is the same for every transfer in the burst.
• The byte lanes that are valid are constant for all beats in the burst. However, within those byte
lanes, the actual bytes that have WSTRB asserted can differ for each beat in the burst.

This burst type is used for repeated accesses to the same location such as when loading or emptying FIFO.

You you mind explaing in details as to what type of interface you are targeting which the AXI encapsulates ?