fix set up time issue

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Chen Zaizhou

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it is said that

Replace buffers with 2 inverters place farther apart

can fix the set up time issue

but why ?
 

Well without flooplan is not easy to understand the constraint.
So the delay could be incremented because the transition time due to the long wire connected to the buffer-output made the setup issue.
Then, by adding a buffer or change the original buffer by two inverters, the wire length is reduced and the transition time is "corrected", instead the tool add an inverter with his own delay.

- - - Updated - - -

You should report the timing the delay before and after with the cap/delay added/slew/ net and cells, to understood the impact.

the slew impact the next cell timing also (reminber, the timing table on the liberty file have on the two axes, the input slew and the output load)
 

thank you so much, rca
but actually my question is to fix the set up time issue, we should reduce the delay,
thus, why not place two inverters close to each other but further to each other,
as we all known that, long wire means more delay
 

yes you should reduce the delay, but if you transition time is very long the delay cell will be also impacted and then the overall delay will faill the setup condition.
by adding an inverter/buffer, the transition time is reduce and the delay cell also, so you win more than you loose by adding this new inverter/buffer.

if you have an example, report the timing with fields "incr, slew...", or open a liberty file and you could see the impact of the slew index on the delay cell.

Code: 
        rise_transition(delay_template_7x7) {
          index_1("0.014049, 0.082537, 0.32294, 0.78203, 1.4973, 2.5008, 3.8214");
          index_2("0.00789691, 0.0172946, 0.0313911, 0.0548852, 0.101873, 0.242838, 0.477779");
          values( \
                 "0.135764, 0.253481, 0.433522, 0.743718, 1.38203, 3.31739, 6.52456", \
                 "0.138143, 0.254341, 0.443457, 0.75025, 1.38315, 3.32158, 6.524", \
                 "0.140257, 0.253461, 0.434096, 0.748193, 1.40933, 3.30704, 6.43956", \
                 "0.148083, 0.258094, 0.439088, 0.75469, 1.38253, 3.2715, 6.6559", \
                 "0.17344, 0.274398, 0.442456, 0.748788, 1.36329, 3.23482, 6.42755", \
                 "0.202586, 0.302638, 0.465972, 0.768936, 1.37065, 3.26529, 6.32773", \
                 "0.243122, 0.332358, 0.480448, 0.77331, 1.3961, 3.23952, 6.33896" \
                 );
        }

Example of buffer drive 1 in TSMC0.18um @ 1V08WC, with index_1 is the slew input, and index_2 is the output cap. You could read, function of the input slew, the cell rise transition goes for the last output cap, from 0.243122ns to 6.33896ns.
 

sorry,rca,
I did not mean adding another inverter,
what i want to say is, in the following two condition, why the second one has the small delay
1. two inverter close to each other
2. two inverter far away from each other.

but thank you though
thank you for your patience
 

Do you report the slew seen by the input connected to the second inverter?
 

I think the buffer replaced with 2 inverters is like this,
>-----------LONG NET------------------> BUFF ---------------LONG NET ----------->
If U divide the wire load and place two inverters, Input transition on 1st inverter and also load on first inverter will reduce..
>----------------------INV1----------------------------INV2------------------------>

Also placing the inverters will reduce the effect of noise.
 

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